Commit Graph

62219 Commits

Author SHA1 Message Date
Rafael Espindola
b29463e006 Don't use getPhysicalRegisterRegClass in PBQP. The existing checks that the
physical register can be allocated in the class of the virtual are sufficient.

I think that the test for virtual registers is more strict than it needs to be,
it should be possible to coalesce two virtual registers the class of one
is a subclass of the other.

llvm-svn: 108118
2010-07-12 01:45:38 +00:00
Chris Lattner
59bffe35a1 fix PR7311 by avoiding breaking casts when a bitcast from scalar->vector
is involved.

llvm-svn: 108117
2010-07-12 01:19:22 +00:00
Chris Lattner
c6f9c11878 make the prototypes for CreateMalloc and CreateFree more consistent. Patch
by Hans Vandierendonck from PR7605

llvm-svn: 108116
2010-07-12 00:57:28 +00:00
Rafael Espindola
0c1a9aa248 Convert the last getPhysicalRegisterRegClass in VirtRegRewriter.cpp to
getMinimalPhysRegClass. It was used to produce spills, and it is better to
use the most specific class if possible.

Update getLoadStoreRegOpcode to handle GR32_AD.

llvm-svn: 108115
2010-07-12 00:52:33 +00:00
Chris Lattner
baef771d17 if jump threading is able to infer interesting values on both
the LHS and RHS of an and/or instruction, don't multiply add
known predecessor values.  This fixes the crash on testcase
from PR7498

llvm-svn: 108114
2010-07-12 00:47:34 +00:00
Chris Lattner
d8288040c3 fix PR7429, a crash turning a load from a string into a float.
llvm-svn: 108113
2010-07-12 00:22:51 +00:00
Chris Lattner
68f5ec0fa2 convert to filechecconvert to filecheckk
llvm-svn: 108112
2010-07-12 00:21:10 +00:00
Chris Lattner
64eeea9044 merge two tests.
llvm-svn: 108111
2010-07-12 00:19:47 +00:00
Chris Lattner
a94ea82dac improve Path::makeUnique when mkstemp/mktemp are not available
patch by Lasse Kärkkäinen in PR7404.

llvm-svn: 108110
2010-07-12 00:09:55 +00:00
Chris Lattner
55bd17a388 change machinelicm to use MachineInstr::isSafeToMove. No
intended functionality change.

The avoidance of hoistiing implicitdef seems wrong though.

llvm-svn: 108109
2010-07-12 00:00:35 +00:00
Chris Lattner
bb04e40482 first part of JIT support for address of labels, part of PR7264,
patch by Yuri!

llvm-svn: 108107
2010-07-11 23:07:28 +00:00
Chris Lattner
666bfc3ab5 introduce WinCOFFObjectWriter, patch by Michael Spencer!
llvm-svn: 108103
2010-07-11 22:07:02 +00:00
Chris Lattner
f2c1a57940 introduce WinCOFFStreamer.cpp, patch by Michael Spencer!
llvm-svn: 108102
2010-07-11 22:05:00 +00:00
Nick Lewycky
9abc58b327 If it's safe to speculatively execute load(alloca) the it's safe to execute
load(gep(alloca)) where the gep is all-zeros. There's more we could do here but
this is a common case.

llvm-svn: 108101
2010-07-11 20:36:29 +00:00
Chris Lattner
656c2c8700 fix typo
llvm-svn: 108100
2010-07-11 19:42:53 +00:00
Jakob Stoklund Olesen
7af3eff94d RISC architectures get their memory operand folding for free.
The only folding these load/store architectures can do is converting COPY into a
load or store, and the target independent part of foldMemoryOperand already
knows how to do that.

llvm-svn: 108099
2010-07-11 19:19:13 +00:00
Jakob Stoklund Olesen
73e71c4703 Use target independent COPY instructions for the fake fextend and fround
operations in x87 code.

llvm-svn: 108098
2010-07-11 18:19:39 +00:00
Jakob Stoklund Olesen
c48892383f Remove redundant branch. Thanks, Anton!
llvm-svn: 108097
2010-07-11 17:17:35 +00:00
Jakob Stoklund Olesen
eeabe43059 Remove obsolete README_SSE note.
We are generating movaps for all XMM register copies, including scalar
floating point values. This is known to be at least as good as movss and movsd
for all known architectures up to and including Nehalem because it avoids a
partial register stall.

The SSEDomainFix pass will switch movaps to movdqa when appropriate (i.e., when
operands come from the integer unit). We don't now that switching movaps to
movapd has any benefit.

The same applies to andps -> pand.

llvm-svn: 108096
2010-07-11 17:13:42 +00:00
Jakob Stoklund Olesen
a28aa26057 Remove TargetInstrInfo::copyRegToReg entirely.
Targets must now implement TargetInstrInfo::copyPhysReg instead. There is no
longer a default implementation forwarding to copyRegToReg.

llvm-svn: 108095
2010-07-11 17:01:17 +00:00
Rafael Espindola
68bbc41d5e Make getPhysicalRegisterRegClass non-virtual. Should be able to remove it soon.
llvm-svn: 108094
2010-07-11 16:49:10 +00:00
Rafael Espindola
a6c4d25f0f Convert uses of getPhysicalRegisterRegClass in VirtRegRewriter.cpp.
The first one was used just to call isSafeToMoveRegClassDefs. In
general, using a more specific reg class is better, in practice only
x86 implements that method and the results are always the same.

The second one is in FindFreeRegister and is used to check if a register
is in a register class, a much more direct call to contains is better as
it should cover more cases and is faster.

llvm-svn: 108093
2010-07-11 16:45:17 +00:00
Jakob Stoklund Olesen
ecdef6c130 Replace copyRegToReg with copyPhysReg for SystemZ.
llvm-svn: 108092
2010-07-11 16:40:46 +00:00
Jakob Stoklund Olesen
040d64f18b Avoid SSE instructions in FastIsel when it is not available.
llvm-svn: 108091
2010-07-11 16:22:13 +00:00
Chandler Carruth
8425bffa25 Remove two other uses of ATTRIBUTE_UNUSED for variables only used within
assert()s, switching to void-casts. Removed an unneeded Compiler.h include as
a result. There are two other uses in LLVM, but they're not due to assert()s,
so I've left them alone.

llvm-svn: 108088
2010-07-11 08:18:12 +00:00
Jakob Stoklund Olesen
8b636d6456 Replace copyRegToReg with copyPhysReg for XCore.
llvm-svn: 108087
2010-07-11 07:56:13 +00:00
Jakob Stoklund Olesen
b8af51cebf Replace copyRegToReg with copyPhysReg for Sparc.
llvm-svn: 108086
2010-07-11 07:56:09 +00:00
Jakob Stoklund Olesen
8a62d7e134 Replace copyRegToReg with copyPhysReg for CellSPU.
llvm-svn: 108084
2010-07-11 07:31:03 +00:00
Jakob Stoklund Olesen
0b1e64c1d4 Replace copyRegToReg with copyPhysReg for PowerPC.
llvm-svn: 108083
2010-07-11 07:31:00 +00:00
Jakob Stoklund Olesen
84ac13069a Fix PIC16 comments referencing copyRegToReg.
llvm-svn: 108082
2010-07-11 07:30:57 +00:00
Jakob Stoklund Olesen
b15ffc7e90 Replace copyRegToReg with copyPhysReg for PIC16.
llvm-svn: 108081
2010-07-11 06:53:33 +00:00
Jakob Stoklund Olesen
fb3525531b Replace copyRegToReg with copyPhysReg for MSP430.
llvm-svn: 108080
2010-07-11 06:53:30 +00:00
Jakob Stoklund Olesen
beb86cfa27 Replace copyRegToReg with copyPhysReg for MBlaze.
llvm-svn: 108079
2010-07-11 06:53:27 +00:00
Jakob Stoklund Olesen
938e41c1fa Replace copyRegToReg with copyPhysReg for ARM.
llvm-svn: 108078
2010-07-11 06:33:54 +00:00
Jakob Stoklund Olesen
18e465659f Replace copyRegToReg with copyPhysReg for Blackfin.
llvm-svn: 108077
2010-07-11 05:44:34 +00:00
Jakob Stoklund Olesen
821d058fd2 X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!
llvm-svn: 108076
2010-07-11 05:44:30 +00:00
Jakob Stoklund Olesen
36d7757d3f Remove copyRegToReg from TargetInstrInfo so it is not longer accesible.
Use a COPY instruction instead for register copies, or TII::copyPhysReg() after
COPY instructions are lowered.

Targets should implement copyPhysReg instead of copyRegToReg.

llvm-svn: 108075
2010-07-11 05:17:06 +00:00
Jakob Stoklund Olesen
08fc7eaaa2 Use COPY in X86FastISel::X86SelectRet.
Don't try a cross-class copy. That is very unlikely anywy since return value
registers are usually register class friendly. (%EAX, %XMM0, etc).

llvm-svn: 108074
2010-07-11 05:17:02 +00:00
Jakob Stoklund Olesen
e2f74d400c Use COPY for fast-isel bitconvert, but don't create cross-class copies.
This doesn't change the behavior of SelectBitcast for X86.

llvm-svn: 108073
2010-07-11 05:16:54 +00:00
Rafael Espindola
84716579d4 Fix va_arg for doubles. With this patch VAARG nodes always contain the
correct alignment information, which simplifies ExpandRes_VAARG a bit.

The patch introduces a new alignment information to TargetLoweringInfo. This is
needed since the two natural candidates cannot be used:

* The 's' in target data: If this is set to the minimal alignment of any
  argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for
  example.
* The getTransientStackAlignment method. It is possible for an architecture to
  have argument less aligned than what we maintain the stack pointer.

llvm-svn: 108072
2010-07-11 04:01:49 +00:00
Jakob Stoklund Olesen
e7d336ee21 Replace copyRegToReg with COPY in FastISelEmitter.
llvm-svn: 108071
2010-07-11 03:53:50 +00:00
Jakob Stoklund Olesen
4b39aa26df Use COPY for extracting ImplicitDef'ed values from fast-isel instructions.
This assumes that the registers can be copied which is probably a safe
assumption.

llvm-svn: 108070
2010-07-11 03:31:05 +00:00
Jakob Stoklund Olesen
57bbaf37c0 Use COPY in FastISel everywhere it is safe and trivial.
The remaining copyRegToReg calls actually check the return value (shock!), so we
cannot trivially replace them with COPY instructions.

llvm-svn: 108069
2010-07-11 03:31:00 +00:00
Jakob Stoklund Olesen
c1aca7464d Replace copyRegToReg with copyPhysReg for Mips.
llvm-svn: 108066
2010-07-11 01:08:31 +00:00
Jakob Stoklund Olesen
0fc69a96b7 Replace copyRegToReg with copyPhysReg for Alpha.
llvm-svn: 108065
2010-07-11 01:08:23 +00:00
Dan Gohman
226e208014 sdiv overflow is outright undefined behavior, with or without the
'exact' keyword. Thanks to nlewycky for pointing this out!

llvm-svn: 108064
2010-07-11 00:08:34 +00:00
Jakob Stoklund Olesen
b1c6191d3b Use COPY in targets
llvm-svn: 108063
2010-07-10 22:43:03 +00:00
Jakob Stoklund Olesen
f0d1bf23eb Replace copyRegToReg with COPY everywhere in lib/CodeGen except for FastISel.
llvm-svn: 108062
2010-07-10 22:42:59 +00:00
Jakob Stoklund Olesen
9b0f71f68f Only collect subreg extracting copies for later coalescing.
This also avoids fatal copies from physregs.

llvm-svn: 108061
2010-07-10 22:42:53 +00:00
Dan Gohman
d96f5d09bb Fix a bug in the code which re-inserts DBG_VALUE nodes after scheduling;
if a block is split (by a custom inserter), the insert point may be in a
different block than it was originally. This fixes 32-bit llvm-gcc
bootstrap builds, and I haven't been able to reproduce it otherwise.

llvm-svn: 108060
2010-07-10 22:42:31 +00:00