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4002 Commits

Author SHA1 Message Date
Torok Edwin
c1017185a5 remove #if 0 code on Bill's request. 
llvm-svn: 63542
 2009-02-02 20:23:02 +00:00
Evan Cheng
16c8f917fb ADD / SUB / SMUL / UMUL with overflow second result top bits must be zero. 
llvm-svn: 63509
 2009-02-02 09:15:04 +00:00
Evan Cheng
e8dfbb5884 Add comment. 
llvm-svn: 63506
 2009-02-02 08:19:07 +00:00
Evan Cheng
483bbd1643 Teach LowerBRCOND to recognize (xor (setcc x), 1). The xor inverts the condition. It's normally transformed by the dag combiner, unless the condition is set by a arithmetic op with overflow. 
llvm-svn: 63505
 2009-02-02 08:07:36 +00:00
Torok Edwin
b4c9a6097f Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for 
var-args, and don't allow FP return values

llvm-svn: 63495
 2009-02-01 18:15:56 +00:00
Duncan Sands
cac6cf74f9 Fix PR3453 and probably a bunch of other potential 
crashes or wrong code with codegen of large integers:
eliminate the legacy getIntegerVTBitMask and
getIntegerVTSignBit methods, which returned their
value as a uint64_t, so couldn't handle huge types.

llvm-svn: 63494
 2009-02-01 18:06:53 +00:00
Dale Johannesen
39738b1ff8 Make LowerCallTo and LowerArguments take a DebugLoc 
argument.  Adjust all callers and overloaded versions.

llvm-svn: 63444
 2009-01-30 23:10:59 +00:00
Bill Wendling
67737da99b Get rid of the non-DebugLoc-ified getNOT() method. 
llvm-svn: 63442
 2009-01-30 23:03:19 +00:00
Mon P Wang
5db99442e4 When PerformBuildVectorCombine, avoid creating a X86ISD::VZEXT_LOAD of 
an illegal type.

llvm-svn: 63380
 2009-01-30 07:07:40 +00:00
Dan Gohman
9d120d6d8f Make x86's BT instruction matching more thorough, and add some 
dagcombines that help it match in several more cases. Add
several more cases to test/CodeGen/X86/bt.ll. This doesn't
yet include matching for BT with an immediate operand, it
just covers more register+register cases.

llvm-svn: 63266
 2009-01-29 01:59:02 +00:00
Mon P Wang
8abb07a527 Fixed lowering of v816 shuffles. 
llvm-svn: 63252
 2009-01-28 23:11:14 +00:00
Duncan Sands
aee16d4916 Rename getAnalysisToUpdate to getAnalysisIfAvailable. 
llvm-svn: 63198
 2009-01-28 13:14:17 +00:00
Evan Cheng
2a965124b7 The memory alignment requirement on some of the mov{h|l}p{d|s} patterns are 16-byte. That is overly strict. These instructions read / write f64 memory locations without alignment requirement. 
llvm-svn: 63195
 2009-01-28 08:35:02 +00:00
Mon P Wang
e1c886f775 Add shuffle splat pattern for x86 sse shifts. 
llvm-svn: 63193
 2009-01-28 08:12:05 +00:00
Dan Gohman
c017343459 Reformat the allocation-order arrays to a more conventional style. 
llvm-svn: 63121
 2009-01-27 19:25:38 +00:00
Dan Gohman
7d80f8688e Simplify findNonImmUse; return the result using the return value 
instead of via a by-reference argument. No functionality change.

llvm-svn: 63118
 2009-01-27 19:04:30 +00:00
Evan Cheng
a05436f739 Implement multiple with overflow by 2 with an add instruction. 
llvm-svn: 63090
 2009-01-27 03:30:42 +00:00
Dan Gohman
2e0343e321 Eliminate unnecessary operands-list traversals. 
llvm-svn: 63088
 2009-01-27 02:37:43 +00:00
Dan Gohman
4ad174b236 Fix the Red Zone calculation for functions with frame pointers. 
Don't use the Red Zone when dynamic stack realignment is needed.
This could be implemented, but most x86-64 ABIs don't require
dynamic stack realignment so it isn't urgent.

llvm-svn: 63074
 2009-01-27 00:40:06 +00:00
Dan Gohman
3a51d8e847 Implement Red Zone utilization on x86-64. This is currently 
disabled by default; I'll enable it when I hook it up with
the llvm-gcc flag which controls it.

llvm-svn: 63056
 2009-01-26 22:22:31 +00:00
Evan Cheng
ec03e0cd3b Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
llvm-svn: 63022
 2009-01-26 18:43:34 +00:00
Dan Gohman
4abaebae0c Take the next steps in making SDUse more consistent with LLVM Use, and 
tidy up SDUse and related code.
 - Replace the operator= member functions with a set method, like
   LLVM Use has, and variants setInitial and setNode, which take
   care up updating use lists, like LLVM Use's does. This simplifies
   code that calls these functions.
 - getSDValue() is renamed to get(), as in LLVM Use, though most
   places can either use the implicit conversion to SDValue or the
   convenience functions instead.
 - Fix some more node vs. value terminology issues.

Also, eliminate the one remaining use of SDOperandPtr, and
SDOperandPtr itself.

llvm-svn: 62995
 2009-01-26 04:35:06 +00:00
Nate Begeman
d2f708eca5 De-identifying per sabre review 
llvm-svn: 62988
 2009-01-26 03:15:31 +00:00
Nate Begeman
92efc4f0ce Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980
 2009-01-26 01:24:32 +00:00
Nate Begeman
81d70f3f54 Support pattern matching various x86 sse shifts. 
llvm-svn: 62979
 2009-01-26 00:52:55 +00:00
Torok Edwin
6f715ebe85 should have removed the + when manually applying a patch! 
llvm-svn: 62973
 2009-01-25 20:29:34 +00:00
Torok Edwin
3f54410405 revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972
 2009-01-25 20:21:24 +00:00
Torok Edwin
49b1d3e3cc If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
llvm-svn: 62967
 2009-01-25 17:58:56 +00:00
Nate Begeman
48f3fe9199 Fix an indent and a typo. 
llvm-svn: 62940
 2009-01-24 22:12:48 +00:00
Chris Lattner
97b6f6a674 hopefully address PR3379 by making the P modifier work in x86 inline asm. 
llvm-svn: 62887
 2009-01-23 22:33:40 +00:00
Bob Wilson
186046e657 Add SelectionDAG::getNOT method to construct bitwise NOT operations, 
corresponding to the "not" and "vnot" PatFrags.  Use the new method
in some places where it seems appropriate.

llvm-svn: 62768
 2009-01-22 17:39:32 +00:00
Evan Cheng
c971801ae1 Eliminate a couple of fields from TargetRegisterClass: SubRegClasses and SuperRegClasses. These are not necessary. Also eliminate getSubRegisterRegClass and getSuperRegisterRegClass. These are slow and their results can change if register file names change. Just use TargetLowering::getRegClassFor() to get the right TargetRegisterClass instead. 
llvm-svn: 62762
 2009-01-22 09:10:11 +00:00
Dan Gohman
29b575c6cd Recognize inline asm for bswap on x86-64 GLIBC. This allows it 
to be supported in the JIT.

llvm-svn: 62730
 2009-01-21 23:40:54 +00:00
Evan Cheng
43d680b0d8 Also favors NOT64r. 
llvm-svn: 62710
 2009-01-21 19:45:31 +00:00
Dan Gohman
704f0d5879 Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691
 2009-01-21 14:50:16 +00:00
Evan Cheng
0ed6a9d7e0 Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661
 2009-01-21 02:09:05 +00:00
Evan Cheng
b3c82db63d Change TargetInstrInfo::isMoveInstr to return source and destination sub-register indices as well. 
llvm-svn: 62600
 2009-01-20 19:12:24 +00:00
Evan Cheng
06cfade044 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
llvm-svn: 62519
 2009-01-19 19:06:11 +00:00
Evan Cheng
a14fd26a8b Minor tweak to LowerUINT_TO_FP_i32. Bias (after scalar_to_vector) has two uses so we should make it the second source operand of ISD::OR so 2-address pass won't have to be smart about commuting. 
%reg1024<def> = MOVSDrm %reg0, 1, %reg0, <cp#0>, Mem:LD(8,8) [ConstantPool + 0]
%reg1025<def> = MOVSD2PDrr %reg1024
%reg1026<def> = MOVDI2PDIrm <fi#-1>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack-1 + 0]
%reg1027<def> = ORPSrr %reg1025<kill>, %reg1026<kill>
%reg1028<def> = MOVPD2SDrr %reg1027<kill>
%reg1029<def> = SUBSDrr %reg1028<kill>, %reg1024<kill>
%reg1030<def> = CVTSD2SSrr %reg1029<kill>
MOVSSmr <fi#0>, 1, %reg0, 0, %reg1030<kill>, Mem:ST(4,4) [FixedStack0 + 0]
%reg1031<def> = LD_Fp32m80 <fi#0>, 1, %reg0, 0, Mem:LD(4,16) [FixedStack0 + 0]
RET %reg1031<kill>, %ST0<imp-use,kill>

The reason 2-addr pass isn't smart enough to commute the ORPSrr is because it can't look pass the MOVSD2PDrr instruction.

llvm-svn: 62505
 2009-01-19 08:19:57 +00:00
Evan Cheng
53e83a2eb9 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

llvm-svn: 62504
 2009-01-19 08:08:22 +00:00
Bill Wendling
ce30a8cab9 Extend thi 
llvm-svn: 62415
 2009-01-17 07:40:19 +00:00
Evan Cheng
182d9c4c9f Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
llvm-svn: 62413
 2009-01-17 07:09:27 +00:00
Bill Wendling
ddd55bdfec Temporarily revert my last change. It is causing a bootstrap failure. 
llvm-svn: 62405
 2009-01-17 04:23:51 +00:00
Bill Wendling
d18c38c0f2 Implement a special algorithm for converting uint_to_fp for i32 values on 
X86. This code:

void f() {
  uint32_t x;
  float y = (float)x;
}

used to be:

     movl     %eax, -8(%ebp)
     movl     [2^52 double], -4(%ebp)
     movsd    -8(%ebp), %xmm0
     subsd    [2^52 double], %xmm0
     cvtsd2ss %xmm0, %xmm0

Is now:

   movsd        [2^52 double], %xmm0
   movsd        %xmm0, %xmm1
   movd         %ecx, %xmm2
   orps         %xmm2, %xmm1
   subsd        %xmm0, %xmm1
   cvtsd2ss     %xmm1, %xmm0

This is faster on X86. Note that there's an extra load of %xmm0 into %xmm1. That
will be fixed in a later coalescer fix.

llvm-svn: 62404
 2009-01-17 03:56:04 +00:00
Bill Wendling
c9e856fbfd Add support for non-zero __builtin_return_address values on X86. 
llvm-svn: 62338
 2009-01-16 19:25:27 +00:00
Mon P Wang
4cfe965df2 Expand insert/extract of a <4 x i32> with a variable index. 
llvm-svn: 62281
 2009-01-15 21:10:20 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Dan Gohman
6fcee67989 Move a few containers out of ScheduleDAGInstrs::BuildSchedGraph 
and into the ScheduleDAGInstrs class, so that they don't get
destructed and re-constructed for each block. This fixes a
compile-time hot spot in the post-pass scheduler.

To help facilitate this, tidy and do some minor reorganization
in the scheduler constructor functions.

llvm-svn: 62275
 2009-01-15 19:20:50 +00:00
Dan Gohman
0b06dcbf4b Add load-folding table entries for BT*ri8 instructions. 
llvm-svn: 62267
 2009-01-15 17:57:09 +00:00
Dan Gohman
37d7b5be33 Make getWidenVectorType const. 
llvm-svn: 62265
 2009-01-15 17:34:08 +00:00