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4790 Commits

Author SHA1 Message Date
Nate Begeman
cbca1b3d14 Another case we could do better on. 
llvm-svn: 26795
 2006-03-16 18:50:44 +00:00
Chris Lattner
b5d0896994 Save/restore VRSAVE once per function, not once per block. 
llvm-svn: 26793
 2006-03-16 18:25:23 +00:00
Chris Lattner
4fd1599ab1 add support for the bitconvert node 
llvm-svn: 26789
 2006-03-16 01:29:53 +00:00
Nate Begeman
e371cb595a Update scheduling info for vrsave instruction 
llvm-svn: 26776
 2006-03-15 05:25:05 +00:00
Chris Lattner
9df7eb4071 add a note 
llvm-svn: 26762
 2006-03-14 19:31:24 +00:00
Chris Lattner
392087f5bd Fix an off by one error that caused PPC LLC failures last night. 
llvm-svn: 26758
 2006-03-14 17:56:49 +00:00
Chris Lattner
80c5fabe4e transformation implemented 
llvm-svn: 26754
 2006-03-14 06:57:34 +00:00
Evan Cheng
ae7469b2c5 PPC LSR pass should use target lowering hooks. 
llvm-svn: 26743
 2006-03-13 23:56:51 +00:00
Evan Cheng
7ec94f2ff7 Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
llvm-svn: 26742
 2006-03-13 23:20:37 +00:00
Evan Cheng
99e87e9147 Update 
llvm-svn: 26741
 2006-03-13 23:19:10 +00:00
Evan Cheng
ed013bd937 Add LSR hooks. 
llvm-svn: 26740
 2006-03-13 23:18:16 +00:00
Chris Lattner
d5ecfd83f1 Handle builtins that directly correspond to GCC builtins. 
llvm-svn: 26737
 2006-03-13 23:09:05 +00:00
Chris Lattner
d0505331d2 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
 2006-03-13 21:52:10 +00:00
Jim Laskey
c741139c24 Handle the removal of the debug chain. 
llvm-svn: 26729
 2006-03-13 13:07:37 +00:00
Chris Lattner
ea1453c3dc remove two implemented items 
llvm-svn: 26728
 2006-03-13 06:52:22 +00:00
Chris Lattner
1782f3971d I can't convince myself that this is safe, remove the recursive call. 
llvm-svn: 26725
 2006-03-13 06:42:16 +00:00
Chris Lattner
3aff8e6acf Fix a couple of bugs that broke the alpha tester build 
llvm-svn: 26722
 2006-03-13 05:23:59 +00:00
Chris Lattner
9898674f99 Handle cracked instructions in dispatch group formation. 
llvm-svn: 26721
 2006-03-13 05:20:04 +00:00
Chris Lattner
ba10d4e4ab Mark instructions that are cracked by the PPC970 decoder as such. 
llvm-svn: 26720
 2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719
 2006-03-12 09:13:49 +00:00
Chris Lattner
19b93158c1 blr is a branch too 
llvm-svn: 26710
 2006-03-11 21:49:49 +00:00
Chris Lattner
916761949b add an example 
llvm-svn: 26709
 2006-03-11 20:20:40 +00:00
Chris Lattner
115b1be710 add a note 
llvm-svn: 26708
 2006-03-11 20:17:08 +00:00
Chris Lattner
2370965e55 teach the JIT to encode vector registers 
llvm-svn: 26697
 2006-03-10 20:19:50 +00:00
Evan Cheng
471bd00cb5 Add option -enable-x86-lsr to enable x86 loop strength reduction pass. 
llvm-svn: 26665
 2006-03-09 21:51:28 +00:00
Chris Lattner
c08825d684 add a note 
llvm-svn: 26661
 2006-03-09 20:13:21 +00:00
Andrew Lenharth
bbf38867f2 these are copies too 
llvm-svn: 26653
 2006-03-09 18:18:51 +00:00
Chris Lattner
e93eeb189f remove some now-dead code 
llvm-svn: 26652
 2006-03-09 18:07:49 +00:00
Andrew Lenharth
f124519fc8 fcopysign for mixed mode 
llvm-svn: 26651
 2006-03-09 17:56:33 +00:00
Andrew Lenharth
2d36f9d389 relax fcopysign 
llvm-svn: 26649
 2006-03-09 17:47:22 +00:00
Andrew Lenharth
e08d165146 alpha and llvm have different oppinions on which arg is the sign bit 
llvm-svn: 26647
 2006-03-09 17:41:50 +00:00
Andrew Lenharth
25de2846c5 Alpha Scheduling classes 
llvm-svn: 26643
 2006-03-09 17:16:45 +00:00
Andrew Lenharth
c180d749a2 fcopysign and get rid of dsnode cruft. custom PA runtimes make this better in some senses 
llvm-svn: 26641
 2006-03-09 14:58:25 +00:00
Andrew Lenharth
78af2795b3 fcopysign support 
llvm-svn: 26640
 2006-03-09 14:57:36 +00:00
Chris Lattner
125881e75b Add support for 'special' llvm globals like debug info and static ctors/dtors. 
llvm-svn: 26628
 2006-03-09 06:14:35 +00:00
Chris Lattner
57acce1443 a couple of miscellaneous things. 
llvm-svn: 26625
 2006-03-09 01:39:46 +00:00
Jim Laskey
84a3db4538 Add #line support for CBE. 
llvm-svn: 26621
 2006-03-08 19:31:15 +00:00
Duraid Madina
a3c5cd22e1 doo de doo 
llvm-svn: 26614
 2006-03-08 06:18:46 +00:00
Chris Lattner
3f23d22d3f Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner
24aa564456 add a note 
llvm-svn: 26605
 2006-03-08 00:25:47 +00:00
Evan Cheng
d73d06f052 X86ISD::REP_STOS and X86ISD::REP_MOVS now produces a flag. 
llvm-svn: 26604
 2006-03-07 23:34:23 +00:00
Evan Cheng
a3e0a7f652 Use rep/stosl; and Count 0x3; rep/stosb for memset with 4 byte aligned dest. 
and variable value.
Similarly for memcpy.

llvm-svn: 26603
 2006-03-07 23:29:39 +00:00
Chris Lattner
4c47b8cd69 Two things: 
1. Don't emit debug info, or other llvm.metadata to the .cbe.c file.
2. Mark static ctors/dtors as such, so that bugpoint works on C++ code
   compiled with the new CFE.

llvm-svn: 26602
 2006-03-07 22:58:23 +00:00
Jim Laskey
91d5ce2531 Use "llvm.metadata" section for debug globals. Filter out these globals in the 
asm printer.

llvm-svn: 26599
 2006-03-07 22:00:35 +00:00
Chris Lattner
27f87a6955 add another missing store. 
llvm-svn: 26595
 2006-03-07 16:26:48 +00:00
Chris Lattner
dfdeec73bc add a couple more load/store instrs, add a newline to the end of file. 
llvm-svn: 26594
 2006-03-07 16:19:46 +00:00
Nate Begeman
a8bc3c0c3c This kinda sorta implements "things that have to lead a dispatch group". 
llvm-svn: 26591
 2006-03-07 08:30:27 +00:00
Chris Lattner
842436586c add some new instructions to the classifier. With this, we correctly insert 
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).

llvm-svn: 26590
 2006-03-07 07:14:55 +00:00
Chris Lattner
0cd4bd574c add some comments that describe what we model 
llvm-svn: 26588
 2006-03-07 06:44:19 +00:00
Chris Lattner
4cd6cd499d Implement a very very simple hazard recognizer for LSU rejects and ctr set/read 
flushes

llvm-svn: 26587
 2006-03-07 06:32:48 +00:00