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462 Commits

Author SHA1 Message Date
Anton Korobeynikov
314ccc5501 Some cheap DAG combine goodness for multiplication with a particular constant. 
This can be extended later on to handle more "complex" constants.

llvm-svn: 103881
 2010-05-15 18:16:59 +00:00
Evan Cheng
16f27a70ef v4i64 and v8i64 are only synthesizable when NEON is available. 
llvm-svn: 103855
 2010-05-15 02:20:21 +00:00
Evan Cheng
85497bd415 Allow TargetLowering::getRegClassFor() to be called on illegal types. Also 
allow target to override it in order to map register classes to illegal
but synthesizable types. e.g. v4i64, v8i64 for ARM / NEON.

llvm-svn: 103854
 2010-05-15 02:18:07 +00:00
Evan Cheng
2af2c9fa14 Added a QQQQ register file to model 4-consecutive Q registers. 
llvm-svn: 103760
 2010-05-14 02:13:41 +00:00
Dan Gohman
fb6f4da0e0 Implement a bunch more TargetSelectionDAGInfo infrastructure. 
Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and
EmitTargetCodeForMemmove out of TargetLowering and into
SelectionDAGInfo to exercise this.

llvm-svn: 103481
 2010-05-11 17:31:57 +00:00
Evan Cheng
11130a0a22 Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction. 
llvm-svn: 103459
 2010-05-11 07:26:32 +00:00
Evan Cheng
7f0d8f1ab0 Model vld2 / vst2 with reg_sequence. 
llvm-svn: 103411
 2010-05-10 17:34:18 +00:00
Jim Grosbach
2db1618b44 Clean up the conditional for handling of sign_extend_inreg based on 
whether the extract instructions are available.

rdar://7956878

llvm-svn: 103277
 2010-05-07 18:34:55 +00:00
Jim Grosbach
e04cc6cb43 Cleanup of ARMv7M support. Move hardware divide and Thumb2 extract/pack 
instructions to subtarget features and update tests to reflect.
PR5717.

llvm-svn: 103136
 2010-05-05 23:44:43 +00:00
Jim Grosbach
3630aff780 Add initial support for ARMv7M subtarget and cortex-m3 cpu. Patch by 
Jordy <snhjordy@gmail.com>.

Followup patches will add some tests and adjust to use Subtarget features
for the instructions.

llvm-svn: 103119
 2010-05-05 20:44:35 +00:00
Evan Cheng
6a76e7d9ae Model CONCAT_VECTORS of two 64-bit values as a REG_SEQUENCE. 
llvm-svn: 103104
 2010-05-05 18:28:36 +00:00
Dan Gohman
68f04d06c8 Get rid of the EdgeMapping map. Instead, just check for BasicBlock 
changes before doing phi lowering for switches.

llvm-svn: 102809
 2010-05-01 00:01:06 +00:00
Dan Gohman
a0f855157e Use const qualifiers with TargetLowering. This eliminates several 
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
 2010-04-17 15:26:15 +00:00
Dan Gohman
5c8db5ab3f Move per-function state out of TargetLowering subclasses and into 
MachineFunctionInfo subclasses.

llvm-svn: 101634
 2010-04-17 14:41:14 +00:00
Bob Wilson
7e53f886d2 Revise my previous change to ExpandBIT_CONVERT. I hadn't realized that this 
may be called when either the source or destination type is i64, and my
change also hadn't fixed the most obvious problem -- assuming that i64 will
only be bitconverted to f64, ignoring the various vector types.
Radar 7873160.

llvm-svn: 101615
 2010-04-17 05:30:19 +00:00
Evan Cheng
c843326d60 Use default lowering of DYNAMIC_STACKALLOC. As far as I can tell, ARM isle is doing the right thing and codegen looks correct for both Thumb and Thumb2. 
llvm-svn: 101410
 2010-04-15 22:20:34 +00:00
Anders Carlsson
32747b3841 Fix build. 
llvm-svn: 101335
 2010-04-15 03:11:28 +00:00
Dan Gohman
0e0b8cf9fd Add const qualifiers to CodeGen's use of LLVM IR constructs. 
llvm-svn: 101334
 2010-04-15 01:51:59 +00:00
Jim Grosbach
92490b077a Add -arm-long-calls option to force calls to be indirect. This makes the 
kernel linker happier when dealing with kexts.

Radar 7805069

llvm-svn: 101303
 2010-04-14 22:28:31 +00:00
Bob Wilson
7b19d89e3a Don't custom lower bit converts to ARM VMOVDRRD or VMOVDRR when the operand 
does not have a legal type.  The legalizer does not know how to handle those
nodes.  Radar 7854640.

llvm-svn: 101282
 2010-04-14 20:45:23 +00:00
Bob Wilson
526e615ff9 Handle a v2f64 formal parameter that is split between registers and memory 
such that the entire second half is in memory.  Radar 7855014.

llvm-svn: 101181
 2010-04-13 22:03:22 +00:00
Bob Wilson
6bc6581ca7 Expand SELECT and SELECT_CC for NEON vector types. 
Radar 7770501.

llvm-svn: 100568
 2010-04-06 22:02:24 +00:00
Mon P Wang
484bbe6aa9 Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100304
 2010-04-04 03:10:48 +00:00
Mon P Wang
0ccf050ca3 Revert r100191 since it breaks objc in clang 
llvm-svn: 100199
 2010-04-02 18:43:02 +00:00
Mon P Wang
a01350755e Reapply address space patch after fixing an issue in MemCopyOptimizer. 
Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset,
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)

llvm-svn: 100191
 2010-04-02 18:04:15 +00:00
Bob Wilson
aae933cc81 Revert Mon Ping's change 99928, since it broke all the llvm-gcc buildbots. 
llvm-svn: 99948
 2010-03-30 22:27:04 +00:00
Mon P Wang
9351ea594a Added support for address spaces and added a isVolatile field to memcpy, memmove, and memset, 
e.g., llvm.memcpy.i32(i8*, i8*, i32, i32) -> llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
A update of langref will occur in a subsequent checkin.

llvm-svn: 99928
 2010-03-30 20:55:56 +00:00
Jim Grosbach
7dc50db8fa tweak the arm if conversion heuristic 
llvm-svn: 99402
 2010-03-24 16:15:14 +00:00
Jim Grosbach
b19d22fcae try being more permissive for if-conversion on ARM V7. see what the nightly 
test run permformance numbers say as to whether it helps.

llvm-svn: 99355
 2010-03-24 00:03:13 +00:00
Bob Wilson
9501c478f7 Revert this change, since it was causing ARM performance regressions. 
--- Reverse-merging r98889 into '.':
U    lib/Target/ARM/ARMInstrNEON.td
U    lib/Target/ARM/ARMISelLowering.h
U    lib/Target/ARM/ARMInstrInfo.td
U    lib/Target/ARM/ARMInstrVFP.td
U    lib/Target/ARM/ARMISelLowering.cpp
U    lib/Target/ARM/ARMInstrFormats.td

llvm-svn: 99010
 2010-03-19 22:51:32 +00:00
Anton Korobeynikov
eeae840ed7 Get rid of target-specific fp <-> int nodes when still I'm here. 
llvm-svn: 98889
 2010-03-18 22:35:45 +00:00
Anton Korobeynikov
23c07f492e Get rid of target-specific nodes for fp16 <-> fp32 conversion. 
llvm-svn: 98888
 2010-03-18 22:35:37 +00:00
Bob Wilson
ac5881b842 Translate "cc" clobber in ARM inline assembly to ARM::CCRRegisterClass. 
Radar 7459078.

llvm-svn: 98586
 2010-03-15 23:09:18 +00:00
Bill Wendling
5493cf6715 Now that the default for Darwin platforms is to place the LSDA into the TEXT 
section, remove the target-specific code that performs this.

llvm-svn: 98580
 2010-03-15 21:09:38 +00:00
Anton Korobeynikov
90fcfccc91 Add substarget feature for FP16 
llvm-svn: 98503
 2010-03-14 18:42:38 +00:00
Anton Korobeynikov
48357cdc62 Add codegen support for FP16 on ARM 
llvm-svn: 98502
 2010-03-14 18:42:31 +00:00
Bill Wendling
c9cfc16363 The ARM EH experiment worked! 
Place the LSDA into the TEXT section for ARM platforms. This involves making the
encoding indirect, pcrel, and sdata4 instead of an absolute pointer. The
references to the type infos are then non-lazy pointers. Revision 98019 changed
the encoding of non-lazy pointers to add the symbol to the non-lazy pointer
definition if it's a local symbol (otherwise, it's external and set to '0' so
that the loader can adjust it to the real value). This paved the way for this
change to work on ARM.

llvm-svn: 98068
 2010-03-09 18:31:07 +00:00
Bill Wendling
344fec6285 This is part of an LLC-beta test used to test <rdar://problem/6804645>. Please 
bear with the awful code. It won't last in its current state beyond tonight.

llvm-svn: 98040
 2010-03-09 02:46:12 +00:00
Bill Wendling
5990930d72 Remove dead parameter passing. 
llvm-svn: 97536
 2010-03-02 01:55:18 +00:00
Bob Wilson
4ffb88d388 Check for comparisons of +/- zero when optimizing less-than-or-equal and 
greater-than-or-equal SELECT_CCs to NEON vmin/vmax instructions.  This is
only allowed when UnsafeFPMath is set or when at least one of the operands
is known to be nonzero.

llvm-svn: 97065
 2010-02-24 22:15:53 +00:00
Jim Grosbach
6f72657d6e LowerCall() should always do getCopyFromReg() to reference the stack pointer. 
Machine instruction selection is much happier when operands are in virtual
registers.

llvm-svn: 97012
 2010-02-24 01:43:03 +00:00
Bob Wilson
84fc0200bd Use NEON vmin/vmax instructions for floating-point selects. 
Radar 7461718.

llvm-svn: 96572
 2010-02-18 06:05:53 +00:00
David Greene
1efa05ab91 Remove an assumption of default arguments. This is in anticipation of a 
change to SelectionDAG build APIs.

llvm-svn: 96230
 2010-02-15 16:55:24 +00:00
Jim Grosbach
a7e098af3b tighten up eh.setjmp sequence a bit. 
llvm-svn: 95603
 2010-02-08 23:22:00 +00:00
Evan Cheng
9057fea7ef Revert 95130. 
llvm-svn: 95160
 2010-02-02 23:55:14 +00:00
Evan Cheng
48375fbf4f Pass callsite return type to TargetLowering::LowerCall and use that to check sibcall eligibility. 
llvm-svn: 95130
 2010-02-02 21:29:10 +00:00
Anton Korobeynikov
f7651ec593 Fix a gross typo: ARMv6+ may or may not support unaligned memory operations. 
Even if they are suported by the core, they can be disabled
(this is just a configuration bit inside some register).

Allow unaligned memops on darwin and conservatively disallow them otherwise.

llvm-svn: 94889
 2010-01-30 14:08:12 +00:00
Evan Cheng
237629e476 Eliminate target hook IsEligibleForTailCallOptimization. 
Target independent isel should always pass along the "tail call" property. Change
target hook LowerCall's parameter "isTailCall" into a refernce. If the target
decides it's impossible to honor the tail call request, it should set isTailCall
to false to make target independent isel happy.

llvm-svn: 94626
 2010-01-27 00:07:07 +00:00
Bob Wilson
5daaa4b21c Wrap some comments to 80 columns. 
llvm-svn: 93940
 2010-01-19 22:56:26 +00:00
Jim Grosbach
70af2216fd Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758
 2010-01-18 19:58:49 +00:00