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462 Commits

Author SHA1 Message Date
Bob Wilson
c01a94dad0 Neon does not support vector divide or remainder. Expand them. 
llvm-svn: 81966
 2009-09-16 00:17:28 +00:00
Bob Wilson
f091792f40 Expand all v2f64 arithmetic operations for Neon. 
Radar 7200803.  (This should also fix the
SingleSource/UnitTests/Vector/sumarray-dbl test.)

llvm-svn: 81959
 2009-09-15 23:55:57 +00:00
Bob Wilson
877a857b4b Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS. 
See the bug report for details.

llvm-svn: 81397
 2009-09-09 23:14:54 +00:00
Anton Korobeynikov
2b6ef7724e Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's. 
llvm-svn: 81262
 2009-09-08 22:51:43 +00:00
Evan Cheng
41e87f2f13 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172. 
llvm-svn: 80904
 2009-09-03 07:04:02 +00:00
Sandeep Patel
9c4e094e2a Retype from unsigned to CallingConv::ID accordingly. Approved by Bob Wilson. 
llvm-svn: 80773
 2009-09-02 08:44:58 +00:00
Bob Wilson
6972a16bbc Add support for generating code for vst{234}lane intrinsics. 
llvm-svn: 80707
 2009-09-01 18:51:56 +00:00
Bob Wilson
bebadd11e4 Generate code for vld{234}_lane intrinsics. 
llvm-svn: 80656
 2009-09-01 04:26:28 +00:00
Jim Grosbach
9a220088ac Clean up LSDA name generation and use for SJLJ exception handling. This 
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.

Objective C++ code could generate function names that broke the previous
scheme. This fixes that.

llvm-svn: 80649
 2009-09-01 01:57:56 +00:00
Anton Korobeynikov
a261afbf14 EXTRACT_VECTOR_ELEMENT can have result type different from element type. 
Remove the assertion and generalize the code for ARM NEON stuff.

llvm-svn: 80498
 2009-08-30 17:14:54 +00:00
Anton Korobeynikov
b2e6f5eed4 Do not assert on too wide splats we don't support. 
llvm-svn: 80409
 2009-08-29 00:08:18 +00:00
Evan Cheng
d7a07ab112 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer. 
llvm-svn: 80404
 2009-08-28 23:18:09 +00:00
Anton Korobeynikov
c1e6083cb8 Hopefully the final missing part :( 
scalar_to_vector is fully legal now

llvm-svn: 80251
 2009-08-27 16:25:49 +00:00
Anton Korobeynikov
33d151e85e Transform float scalar_to_vector into subreg accesses. 
No idea whether this is profitable or not.

llvm-svn: 80245
 2009-08-27 14:38:44 +00:00
Bob Wilson
5240e9de02 Remove unneeded ARM-specific DAG nodes for VLD* and VST* Neon operations. 
The instructions can be selected directly from the intrinsics.  We will need
to add some ARM-specific nodes for VLD/VST of 3 and 4 128-bit vectors, but
those are not yet implemented.

llvm-svn: 80117
 2009-08-26 17:39:53 +00:00
Anton Korobeynikov
1c904039ce Expand scalar_to_vector - we don't have any isel logic for it now 
llvm-svn: 80107
 2009-08-26 16:26:09 +00:00
Eli Friedman
79615641f1 Make x86 test actually test x86 code generation. Fix the 
construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.

llvm-svn: 79719
 2009-08-22 03:13:10 +00:00
Bob Wilson
6d4400e852 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, 
now using shuffles instead of intrinsics.

llvm-svn: 79673
 2009-08-21 20:54:19 +00:00
Anton Korobeynikov
20d832fa1b Fix some typos and use type-based isel for VZIP/VUZP/VTRN 
llvm-svn: 79625
 2009-08-21 12:41:42 +00:00
Anton Korobeynikov
218db4a01c Add lowering of ARM 4-element shuffles to multiple instructios via perfectshuffle-generated table. 
llvm-svn: 79624
 2009-08-21 12:41:24 +00:00
Anton Korobeynikov
220512160d Add nodes & dummy matchers for some v{zip,uzp,trn} instructions 
llvm-svn: 79622
 2009-08-21 12:40:50 +00:00
Anton Korobeynikov
dccf7cb911 Expand EXTRACT_SUBVECTOR 
llvm-svn: 79621
 2009-08-21 12:40:35 +00:00
Anton Korobeynikov
f6657d5e02 Provide vext.{16,32} 
llvm-svn: 79620
 2009-08-21 12:40:21 +00:00
Anton Korobeynikov
a2e4bc2312 Use masks not nodes for vector shuffle predicates. Provide set of 'legal' masks, so legalizer won't infinite cycle 
llvm-svn: 79619
 2009-08-21 12:40:07 +00:00
Bob Wilson
fae9057bf0 Add support for Neon VEXT (vector extract) shuffles. 
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428
 2009-08-19 17:03:43 +00:00
Bill Wendling
962adec4ee Reapply r79127. It was fixed by d0k. 
llvm-svn: 79136
 2009-08-15 21:21:19 +00:00
Bill Wendling
bfebbb6477 Revert r79127. It was causing compilation errors. 
llvm-svn: 79135
 2009-08-15 21:14:01 +00:00
Evan Cheng
5d841097a9 Change allowsUnalignedMemoryAccesses to take type argument since some targets 
support unaligned mem access only for certain types. (Should it be size
instead?)

ARM v7 supports unaligned access for i16 and i32, some v6 variants support it
as well.

llvm-svn: 79127
 2009-08-15 19:23:44 +00:00
Evan Cheng
9d351a7246 Turn on if-conversion for thumb2. 
llvm-svn: 79084
 2009-08-15 07:59:10 +00:00
Anton Korobeynikov
3a0cde8c91 Allow targets to specify their choice of calling conventions per 
libcall. Take advantage of this in the ARM backend to rectify broken
choice of CC when hard float is in effect. PIC16 may want to see if
it could be of use in MakePIC16Libcall, which works unchanged.

Patch by Sandeep!

llvm-svn: 79033
 2009-08-14 20:10:52 +00:00
Evan Cheng
67fd47b38b Add Thumb2 lsr hooks. 
llvm-svn: 79032
 2009-08-14 20:09:37 +00:00
Evan Cheng
ebbcd00c17 80 col violation. 
llvm-svn: 79026
 2009-08-14 19:11:20 +00:00
Bob Wilson
80db08baec Now that all the legal Neon shuffles (or at least the ones that have been 
implemented so far) are recognized during legalization, it is easy to fall
back to the default expansion for other shuffles.

llvm-svn: 78995
 2009-08-14 05:16:33 +00:00
Bob Wilson
d337cde6e5 Create a new ARM-specific DAG node, VDUP, to represent a splat from a 
scalar_to_vector.  Generate these VDUP nodes during legalization instead
of trying to recognize the pattern during selection.

llvm-svn: 78994
 2009-08-14 05:13:08 +00:00
Bob Wilson
7a311914ab During legalization, change Neon vdup_lane operations from shuffles to 
target-specific VDUPLANE nodes.  This allows the subreg handling for the
quad-register version to be done easily with Pats in the .td file, instead
of with custom code in ARMISelDAGToDAG.cpp.

llvm-svn: 78993
 2009-08-14 05:08:32 +00:00
Owen Anderson
9df206d02d Push LLVMContexts through the IntegerType APIs. 
llvm-svn: 78948
 2009-08-13 21:58:54 +00:00
Bob Wilson
e3eedf3cd2 Add a fixme message about canonicalizing floating-point vector types. 
llvm-svn: 78897
 2009-08-13 06:01:30 +00:00
Bob Wilson
8cb7da85e3 Revert r78852 for now. I want to do this differently, but I don't have time 
to fix it tonight.

llvm-svn: 78896
 2009-08-13 05:58:56 +00:00
Bob Wilson
2940b8e9a5 Add a comment to describe why vector shuffles are legalized to custom DAG nodes. 
llvm-svn: 78884
 2009-08-13 02:13:04 +00:00
Bob Wilson
11ee30bdc8 Use cast<> instead of dyn_cast<> in places where the type is known. 
llvm-svn: 78881
 2009-08-13 01:57:47 +00:00
Bob Wilson
b089d07a1f Recognize Neon VDUP shuffles during legalization instead of selection. 
llvm-svn: 78852
 2009-08-12 22:54:19 +00:00
Bob Wilson
d8b7ca4c28 Recognize Neon VREV shuffles during legalization instead of selection. 
llvm-svn: 78850
 2009-08-12 22:31:50 +00:00
Jim Grosbach
74c682dde4 Add catch block handling to SjLj exception handling. 
llvm-svn: 78817
 2009-08-12 17:38:44 +00:00
Evan Cheng
c369ccbe83 Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while 
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
 2009-08-11 20:47:22 +00:00
Jim Grosbach
3c898a99bd Whitespace cleanup. Remove trailing whitespace. 
llvm-svn: 78666
 2009-08-11 15:33:49 +00:00
Bob Wilson
d64e304671 Use vAny type to get rid of Neon intrinsics that differed only in whether 
the overloaded vector types allowed floating-point or integer vector elements.
Most of these operations actually depend on the element type, so bitcasting
was not an option.

If you include the vpadd intrinsics that I updated earlier, this gets rid
of 20 intrinsics.

llvm-svn: 78646
 2009-08-11 05:39:44 +00:00
Jim Grosbach
c9a1dd9291 SjLj based exception handling unwinding support. This patch is nasty, brutish 
and short. Well, it's kinda short. Definitely nasty and brutish.

The front-end generates the register/unregister calls into the SjLj runtime,
call-site indices and landing pad dispatch. The back end fills in the LSDA
with the call-site information provided by the front end. Catch blocks are
not yet implemented.

Built on Darwin and verified no llvm-core "make check" regressions.

llvm-svn: 78625
 2009-08-11 00:09:57 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type. 
llvm-svn: 78610
 2009-08-10 22:56:29 +00:00
Owen Anderson
30bf6c8dab SimpleValueType-ify a few more methods on TargetLowering. 
llvm-svn: 78595
 2009-08-10 20:46:15 +00:00