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4783 Commits

Author SHA1 Message Date
Duncan Sands
d3859c83a5 Simplify using getIntPtrConstant. 
llvm-svn: 48355
 2008-03-14 05:23:57 +00:00
Nate Begeman
f06c08e652 Tabs -> spaces 
Use getIntPtrConstant in a couple places to shorten stuff up
Handle splitting vector shuffles with undefs in the mask

llvm-svn: 48351
 2008-03-14 00:53:31 +00:00
Evan Cheng
1ce3ba341d Livein copy scheduling fixes: do not coalesce physical register copies, correctly determine the safe location to insert the copies. 
llvm-svn: 48348
 2008-03-14 00:14:55 +00:00
Dan Gohman
486f664806 More APInt-ification. 
llvm-svn: 48344
 2008-03-13 22:13:53 +00:00
Evan Cheng
b479bf0d0c Undo tweak. It had no obvious benefit. 
llvm-svn: 48341
 2008-03-13 17:42:48 +00:00
Evan Cheng
a7c38d1ce9 Typo. 
llvm-svn: 48337
 2008-03-13 08:04:35 +00:00
Evan Cheng
9a7395ba78 Don't try to sink 3-address instruction if convertToThreeAddress created more than one instructions. 
llvm-svn: 48336
 2008-03-13 07:56:58 +00:00
Evan Cheng
38a8da7b16 Remove an unused command line option. 
llvm-svn: 48334
 2008-03-13 06:38:28 +00:00
Evan Cheng
0b8b1647dd TwoAddressInstructionPass enhancement. After it converts a two address instruction into a 3-address one, sink it past the instruction that kills the read-mod-write register if its definition is used past the kill. This reduces the number of live register by one. 
llvm-svn: 48333
 2008-03-13 06:37:55 +00:00
Christopher Lamb
0f1c32eb63 Get rid of a pseudo instruction and replace it with subreg based operation on real instructions, ridding the asm printers of the hack used to do this previously. In the process, update LowerSubregs to be careful about eliminating copies that have side affects. 
Note: the coalescer will have to be careful about this too, when it starts coalescing insert_subreg nodes.
llvm-svn: 48329
 2008-03-13 05:47:01 +00:00
Evan Cheng
6b57844f0c Remove unused options. 
llvm-svn: 48319
 2008-03-13 02:41:34 +00:00
Evan Cheng
b9fc5d6d07 Refactor some code out of MachineSink into a MachineInstr query. 
llvm-svn: 48311
 2008-03-13 00:44:09 +00:00
Evan Cheng
620fd19798 Experimental scheduler change to schedule / coalesce the copies added for function livein's. Take 2008-03-10-RegAllocInfLoop.ll, the schedule looks like this after these copies are inserted: 
entry: 0x12049d0, LLVM BB @0x1201fd0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1028<def> = MOV32rr %EAX
        %reg1029<def> = MOV32rr %EDX
        %reg1030<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x1201910 + 0]
        %reg1025<def> = MOV32rr %reg1029
        %reg1026<def> = MOV32rr %reg1030
        %reg1024<def> = MOV32rr %reg1028

The copies unnecessarily increase register pressure and it will end up requiring a physical register to be spilled.

With -schedule-livein-copies:
entry: 0x12049d0, LLVM BB @0x1201fa0, ID#0:
Live Ins: %EAX %EDX %ECX
        %reg1031<def> = MOVPC32r 0
        %reg1032<def> = ADD32ri %reg1031, <es:_GLOBAL_OFFSET_TABLE_>, %EFLAGS<imp-def>
        %reg1024<def> = MOV32rr %EAX
        %reg1025<def> = MOV32rr %EDX
        %reg1026<def> = MOV32rr %ECX
        %reg1027<def> = MOV8rm %reg0, 1, %reg0, 0, Mem:LD(1,1) [0x12018e0 + 0]

Much better!

llvm-svn: 48307
 2008-03-12 22:19:41 +00:00
Duncan Sands
f830ed681b Initial soft-float support for LegalizeTypes. I rewrote 
the fcopysign expansion from LegalizeDAG to get rid of
what seems to be a bug: the use of sign extension means
that when copying the sign bit from an f32 to an f64,
the upper 32 bits of the f64 (now an i64) are set, not
just the top bit...  I also generalized it to work for
any sized floating point types, and removed the bogosity:
  SDOperand Mask1 = (SrcVT == MVT::f64)
    ? DAG.getConstantFP(BitsToDouble(1ULL << 63), SrcVT)
    : DAG.getConstantFP(BitsToFloat(1U << 31), SrcVT);
  Mask1 = DAG.getNode(ISD::BIT_CONVERT, SrcNVT, Mask1);
(here SrcNVT is an integer with the same size as SrcVT).
As far as I can see this takes a 1 << 63, converts to
a double, converts that to a floating point constant
then converts that to an integer constant, ending up
with... 1 << 63 as an integer constant!  So I just
generate this integer constant directly.

llvm-svn: 48305
 2008-03-12 21:27:04 +00:00
Dan Gohman
e40582180e Change VirtRegMap's dump to dump to cerr, not DOUT, so that it 
can be called from within a debuger without having -debug specified
on the command-line.

llvm-svn: 48298
 2008-03-12 20:52:10 +00:00
Dan Gohman
4e4f2e2ba4 Fix typos in comments. 
llvm-svn: 48297
 2008-03-12 20:50:04 +00:00
Duncan Sands
f9de87eae8 Fix typo. 
llvm-svn: 48295
 2008-03-12 20:35:19 +00:00
Duncan Sands
05eb212b2d Don't try to extract an i32 from an f64. This 
getCopyToParts problem was noticed by the new
LegalizeTypes infrastructure.  In order to avoid
this kind of thing in the future I've added a
check that EXTRACT_ELEMENT is only used with
integers.  Once LegalizeTypes is up and running
most likely BUILD_PAIR and EXTRACT_ELEMENT can
be removed, in favour of using apints instead.

llvm-svn: 48294
 2008-03-12 20:30:08 +00:00
Evan Cheng
df92afe7d3 Clean up my own mess. 
X86 lowering normalize vector 0 to v4i32. However DAGCombine can fold (sub x, x) -> 0 after legalization. It can create a zero vector of a type that's not expected (e.g. v8i16). We don't want to disable the optimization since leaving a (sub x, x) is really bad. Add isel patterns for other types of vector 0 to ensure correctness. It's highly unlikely to happen other than in bugpoint reduced test cases.

llvm-svn: 48279
 2008-03-12 07:02:50 +00:00
Owen Anderson
df98435a16 We also need to collect the VN IDs for the PHI instructions for later updating. 
llvm-svn: 48278
 2008-03-12 04:22:57 +00:00
Owen Anderson
ecc3b561eb When we're determining what registers to coallesce, track the VNInfo IDs for the definitions that 
feed the PHI instructions.  We'll need these IDs in order to update LiveIntervals properly.

llvm-svn: 48277
 2008-03-12 03:13:29 +00:00
Evan Cheng
ee092b2dfc Total brain cramp. 
llvm-svn: 48274
 2008-03-12 02:05:05 +00:00
Evan Cheng
1812351f99 Set NextMII after issuing a physical register spill. 
llvm-svn: 48263
 2008-03-12 00:14:07 +00:00
Evan Cheng
909992f970 Minor debug output bug. 
llvm-svn: 48261
 2008-03-12 00:02:46 +00:00
Anton Korobeynikov
55f54ba252 Correctly propagate thread-local flag from aliasee to alias. This fixes PR2137 
llvm-svn: 48257
 2008-03-11 22:38:53 +00:00
Dan Gohman
8e3c88c4e9 Use PassManagerBase instead of FunctionPassManager for functions 
that merely add passes. This allows them to be used with either
FunctionPassManager or PassManager, or even with a custom new
kind of pass manager.

llvm-svn: 48256
 2008-03-11 22:29:46 +00:00
Anton Korobeynikov
aa1433ab47 Honour aliases visibility during asm emission 
llvm-svn: 48249
 2008-03-11 21:41:14 +00:00
Evan Cheng
665363494f Transfer physical register spill info when load / store folding happens. 
llvm-svn: 48246
 2008-03-11 21:34:46 +00:00
Dan Gohman
1fece90de9 Use the correct value for InSignBit. 
llvm-svn: 48245
 2008-03-11 21:29:43 +00:00
Dan Gohman
55a443d612 Initial codegen support for functions and calls with multiple return values. 
llvm-svn: 48244
 2008-03-11 21:11:25 +00:00
Christopher Lamb
74f4d837df Recommitting parts of r48130. These do not appear to cause the observed failures. 
llvm-svn: 48223
 2008-03-11 10:09:17 +00:00
Evan Cheng
794f4ee703 Use TargetRegisterInfo::getPhysicalRegisterRegClass. Remove duplicated code. 
llvm-svn: 48221
 2008-03-11 07:55:13 +00:00
Evan Cheng
af1c76846d When the register allocator runs out of registers, spill a physical register around the def's and use's of the interval being allocated to make it possible for the interval to target a register and spill it right away and restore a register for uses. This likely generates terrible code but is before than aborting. 
llvm-svn: 48218
 2008-03-11 07:19:34 +00:00
Duncan Sands
1b059ad5d5 Some LegalizeTypes code factorization and minor 
enhancements.

llvm-svn: 48215
 2008-03-11 06:41:14 +00:00
Chris Lattner
3241d0df37 compile: double test() {} 
into:

_test:
	fldz
	ret

instead of:

_test:
	subl	$12, %esp
	#IMPLICIT_DEF %xmm0
	movsd	%xmm0, (%esp)
	fldl	(%esp)
	addl	$12, %esp
	ret

llvm-svn: 48213
 2008-03-11 06:21:08 +00:00
Chris Lattner
e58af59475 variadic instructions don't have operand info for variadic arguments. 
llvm-svn: 48208
 2008-03-11 03:14:42 +00:00
Dan Gohman
85bfbe2293 Generalize ExpandIntToFP to handle the case where the operand is legal 
and it's the result that requires expansion. This code is a little confusing
because the TargetLoweringInfo tables for [US]INT_TO_FP use the operand type
(the integer type) rather than the result type. 

llvm-svn: 48206
 2008-03-11 01:59:03 +00:00
Chris Lattner
98af9eac5f If a register operand comes from the variadic part of a node, don't 
verify the register constraint matches what the instruction expects.

llvm-svn: 48205
 2008-03-11 00:59:28 +00:00
Evan Cheng
77df19cb8c Temporarily revert 48175. 
llvm-svn: 48204
 2008-03-11 00:27:34 +00:00
Dan Gohman
1a65335a9b More APInt-ification. 
llvm-svn: 48201
 2008-03-11 00:11:06 +00:00
Dan Gohman
65bfbfb8dd Correctly clone FlaggedNodes. 
llvm-svn: 48196
 2008-03-10 23:48:14 +00:00
Dan Gohman
7f8c939777 APInt-ify this. 
llvm-svn: 48194
 2008-03-10 23:38:17 +00:00
Dan Gohman
67aed9bbb0 Implement more support for fp-to-i128 and i128-to-fp conversions. 
llvm-svn: 48189
 2008-03-10 23:03:31 +00:00
Evan Cheng
863da1c28c If the register allocator ran out of registers, just abort for now. 
llvm-svn: 48175
 2008-03-10 21:27:20 +00:00
Dan Gohman
47137eba06 Fix mul expansion to check the correct number of bits for 
zero extension when checking if an unsigned multiply is
safe.

llvm-svn: 48171
 2008-03-10 20:42:19 +00:00
Evan Cheng
8b8d58e1aa Somewhat better solution. 
llvm-svn: 48170
 2008-03-10 19:58:22 +00:00
Evan Cheng
7d9e5a7680 Default ISD::PREFETCH to expand. 
llvm-svn: 48169
 2008-03-10 19:38:10 +00:00
Evan Cheng
067ecbc341 Revert 48125, 48126, and 48130 for now to unbreak some x86-64 tests. 
llvm-svn: 48167
 2008-03-10 19:31:26 +00:00
Scott Michel
bb8e8fca47 Give TargetLowering::getSetCCResultType() a parameter so that ISD::SETCC's 
return ValueType can depend its operands' ValueType.

This is a cosmetic change, no functionality impacted.

llvm-svn: 48145
 2008-03-10 15:42:14 +00:00
Bill Wendling
91ff268a77 Minor cleanup. No functionality change. 
llvm-svn: 48142
 2008-03-10 08:13:01 +00:00