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7052 Commits

Author SHA1 Message Date
Bill Wendling
d43819da2f Fix so that pandn is emitted instead of an xor/and combo. Add integer 
comparison operators.

llvm-svn: 35385
 2007-03-27 20:22:40 +00:00
Lauro Ramos Venancio
99fca527d3 "The C standards do say that "char" may either be a "signed char" or "unsigned 
char" and it is up to the compilers implementation or the platform which is
followed."
http://www.arm.linux.org.uk/docs/faqs/signedchar.php

llvm-svn: 35382
 2007-03-27 16:33:08 +00:00
Lauro Ramos Venancio
8b2e32de5a bugfix: sometimes the spiller puts a load between the "mov lr, pc" and "bx" of a CALL_NOLINK. 
llvm-svn: 35381
 2007-03-27 16:19:21 +00:00
Evan Cheng
968135bd3f findRegisterUseOperand() changed. 
llvm-svn: 35366
 2007-03-26 22:41:48 +00:00
Bill Wendling
8065cc3173 Promote to v1i64 type... 
llvm-svn: 35353
 2007-03-26 08:03:33 +00:00
Bill Wendling
3c4e130b77 Updated. 
llvm-svn: 35352
 2007-03-26 07:55:58 +00:00
Bill Wendling
a42484728c Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351
 2007-03-26 07:53:08 +00:00
Anton Korobeynikov
a5e854461f Fix authorship 
llvm-svn: 35337
 2007-03-25 13:44:26 +00:00
Chris Lattner
ee90a087a6 add a note 
llvm-svn: 35334
 2007-03-25 05:10:46 +00:00
Chris Lattner
6d8bbccee0 add a note 
llvm-svn: 35330
 2007-03-25 04:46:28 +00:00
Chris Lattner
31c6763051 Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll 
llvm-svn: 35329
 2007-03-25 04:44:03 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Chris Lattner
18c3c6a01d Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
llvm-svn: 35320
 2007-03-25 02:01:03 +00:00
Chris Lattner
104e73382c enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Chris Lattner
92e2ee7b2d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35318
 2007-03-25 01:44:57 +00:00
Chris Lattner
a04981fbda add a bad case evan though of. 
llvm-svn: 35296
 2007-03-24 06:01:32 +00:00
Anton Korobeynikov
63bff8af0c Autodetect MMX & SSE stuff for AMD processors 
llvm-svn: 35292
 2007-03-23 23:46:48 +00:00
Bill Wendling
124f2c8706 PR1260: 
Add final support to get the QT example to compile.

llvm-svn: 35290
 2007-03-23 22:35:46 +00:00
Bill Wendling
e6a9c6dfe6 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.

llvm-svn: 35269
 2007-03-22 20:29:26 +00:00
Bill Wendling
1bcad4c1cd Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Anton Korobeynikov
c0842af02d Add TODO list for MSIL backend 
llvm-svn: 35244
 2007-03-21 21:48:59 +00:00
Anton Korobeynikov
bc43d296b2 Let the new backend begin! 
llvm-svn: 35242
 2007-03-21 21:38:25 +00:00
Dale Johannesen
fb7b59f5dd add generation of unnecessary push/pop around calls 
llvm-svn: 35241
 2007-03-21 21:16:39 +00:00
Nicolas Geoffray
205541ef78 Protect R31's frame offset from being used by callee-saved registers, when R31 
is the frame pointer.

llvm-svn: 35233
 2007-03-21 16:44:14 +00:00
Evan Cheng
00a5cbf9e7 Mark re-materializable instructions. 
llvm-svn: 35230
 2007-03-21 00:16:56 +00:00
Evan Cheng
fb9c4c2edc Updated. 
llvm-svn: 35229
 2007-03-20 22:32:39 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid 
instructions (that would have to be split later)

llvm-svn: 35227
 2007-03-20 21:54:54 +00:00
Lauro Ramos Venancio
11d7d3fcaf bugfix: When the source register of CALL_NOLINK was LR, the following code was emitted: 
mov lr, pc
    bx lr
So, the function was not called.

llvm-svn: 35218
 2007-03-20 17:57:23 +00:00
Evan Cheng
4fec9d7228 Make two piece constant generation as a single instruction. It's re-materialized as a load from constantpool. 
llvm-svn: 35207
 2007-03-20 08:11:30 +00:00
Evan Cheng
11976abd1e New entry. 
llvm-svn: 35206
 2007-03-20 08:10:17 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner
b9cc0ade43 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner
1ed603c0d9 fix indentation 
llvm-svn: 35202
 2007-03-20 02:25:53 +00:00
Dale Johannesen
c526b970ce fix obvious comment bug 
llvm-svn: 35196
 2007-03-20 00:30:56 +00:00
Evan Cheng
8d374caead Fix naming inconsistencies. 
llvm-svn: 35163
 2007-03-19 07:48:02 +00:00
Evan Cheng
7cbf4c4582 Special LDR instructions to load from non-pc-relative constantpools. These are 
rematerializable. Only used for constant generation for now.

llvm-svn: 35162
 2007-03-19 07:20:03 +00:00
Evan Cheng
389cf8e719 Constant generation instructions are re-materializable. 
llvm-svn: 35161
 2007-03-19 07:09:02 +00:00
Evan Cheng
498f19548c Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Chris Lattner
59fe2be1c4 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Chris Lattner
a1df6908d2 minor updates 
llvm-svn: 35143
 2007-03-18 22:41:33 +00:00
Nick Lewycky
04ecc07c25 This is implemented. We now generate: 
entry:
        icmp ugt i32 %x, 4              ; <i1>:0 [#uses=1]
        br i1 %0, label %cond_true, label %cond_false

cond_true:              ; preds = %entry
        %tmp1 = tail call i32 (...)* @bar( i32 12 )             ; <i32> [#uses=0]
        ret void

cond_false:             ; preds = %entry
        switch i32 %x, label %cond_true15 [
                 i32 4, label %cond_true3
                 i32 3, label %cond_true7
                 i32 2, label %cond_true11
                 i32 0, label %cond_false17
        ]

...

llvm-svn: 35142
 2007-03-18 14:37:20 +00:00
Devang Patel
2dabb16eac Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Lauro Ramos Venancio
f756184c5e Only ARMv6 has BSWAP. 
Fix MultiSource/Applications/aha test.

llvm-svn: 35128
 2007-03-16 22:54:16 +00:00
Bill Wendling
8ced23ee5a And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Evan Cheng
4858c6f781 Added isLegalAddressExpression(). Only allows X +/- C for now. 
llvm-svn: 35122
 2007-03-16 08:43:56 +00:00
Bill Wendling
feaff80149 Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng
00edaa08b5 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712 Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Evan Cheng
50a0af3b57 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00