181938 Commits

Author SHA1 Message Date
Francis Visoiu Mistrih
d9a26939d3 [Remarks] Simplify and refactor the RemarkParser interface
Before, everything was based on some kind of type erased parser
implementation which container a lot of boilerplate code when multiple
formats were to be supported.

This simplifies it by:

* the remark now owns its arguments
* *always* returning an error from the implementation side
* working around the way the YAML parser reports errors: catch them through
callbacks and re-insert them in a proper llvm::Error
* add a CParser wrapper that is used when implementing the C API to
avoid cluttering the C++ API with useless state
* LLVMRemarkParserGetNext now returns an object that needs to be
released to avoid leaking resources
* add a new API to dispose of a remark entry: LLVMRemarkEntryDispose

llvm-svn: 366217
2019-07-16 15:25:05 +00:00
Francis Visoiu Mistrih
08f879c89c [Remarks][NFC] Combine ParserFormat and SerializerFormat
It's useless to have both.

llvm-svn: 366216
2019-07-16 15:24:59 +00:00
Amara Emerson
2402efd785 [ADCE] Fix non-deterministic behaviour due to iterating over a pointer set.
Original patch by Yann Laigle-Chapuy

Differential Revision: https://reviews.llvm.org/D64785

llvm-svn: 366215
2019-07-16 15:23:10 +00:00
Amaury Sechet
f1904bd7ad [DAGCombiner] fold (addcarry (xor a, -1), b, c) -> (subcarry b, a, !c) and flip carry.
Summary:
As per title. DAGCombiner only mathes the special case where b = 0, this patches extends the pattern to match any value of b.

Depends on D57302

Reviewers: hfinkel, RKSimon, craig.topper

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59208

llvm-svn: 366214
2019-07-16 15:17:00 +00:00
Matt Arsenault
8e480a8a3d AMDGPU/GlobalISel: Fix test failures in release build
Apparently the check for legal instructions during instruction
select does not happen without an asserts build, so these would
successfully select in release, and fail in debug.

Make s16 and/or/xor legal. These can just be selected directly
to the 32-bit operation, as is already done in SelectionDAG, so just
make them legal.

llvm-svn: 366210
2019-07-16 14:28:30 +00:00
Owen Reynolds
87d8186b4e [llvm-ar][test] Add to llvm-ar test coverage
This change adds tests to cover existing llvm-ar functionality.
print.test is omitted due to failing on Darwin.

Differential Revision: https://reviews.llvm.org/D64330

llvm-svn: 366209
2019-07-16 14:25:37 +00:00
Owen Reynolds
4f9a709310 Reapply [llvm-ar][test] Increase llvm-ar test coverage
This reapplies 365316 without extract.test due to failing on Darwin.

Differential Revision: https://reviews.llvm.org/D63935

llvm-svn: 366206
2019-07-16 12:53:59 +00:00
Sylvestre Ledru
5622edf8ed remove a duplicate declaration
llvm-svn: 366205
2019-07-16 12:05:54 +00:00
Sylvestre Ledru
cdbbe489dd Document the LLVM_ENABLE_BINDINGS option
llvm-svn: 366204
2019-07-16 11:59:17 +00:00
George Rimar
3781086e1e [Object/llvm-readelf/llvm-readobj] - Improve error reporting when e_shstrndx is broken.
When e_shstrndx is broken, it is impossible to get a section name.
In this patch I improved the error message we show and 
added tests for Object and for llvm-readelf/llvm-readobj

Message was changed in two places:
1) llvm-readelf/llvm-readobj previously used a code from Object/ELF.h,
now they have a modified version of it (it has less checks and allows
dumping broken things).
2) Code in Object/ELF.h is still used for generic cases.

Differential revision: https://reviews.llvm.org/D64714

llvm-svn: 366203
2019-07-16 11:07:30 +00:00
Owen Reynolds
a4d3a83623 Reapply [llvm-ar][test] Add to MRI test coverage
This reapplies 363232 without mri-utf8.test due to failing on Darwin.

Differential Revision: https://reviews.llvm.org/D63197

llvm-svn: 366201
2019-07-16 11:02:11 +00:00
Sam McCall
da8874b9a8 Remove username from git-llvm script, erroneously added in 366197
llvm-svn: 366198
2019-07-16 10:14:53 +00:00
Kyrylo Tkachov
c4056176b9 [AArch64] Implement __jcvt intrinsic from Armv8.3-A
The jcvt intrinsic defined in ACLE [1] is available when ARM_FEATURE_JCVT is defined.

This change introduces the AArch64 intrinsic, wires it up to the instruction and a new clang builtin function.
The __ARM_FEATURE_JCVT macro is now defined when an Armv8.3-A or higher target is used.
I've implemented the target detection logic in Clang so that this feature is enabled for architectures from armv8.3-a onwards (so -march=armv8.4-a also enables this, for example).

make check-all didn't show any new failures.

[1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics

Differential Revision: https://reviews.llvm.org/D64495

llvm-svn: 366197
2019-07-16 09:27:39 +00:00
Kyrylo Tkachov
4209e96014 [NFC] Test commit: add full stop at end of comment
llvm-svn: 366195
2019-07-16 09:15:01 +00:00
Zi Xuan Wu
ec5cafc44c [NFC][PowerPC] Add test case for D64195
llvm-svn: 366191
2019-07-16 07:54:47 +00:00
Igor Kudrin
c707e71aa1 [DWARF] Fix the reserved values for unit length in DWARFDebugLine.
The DWARF3 documentation had inconsistency concerning the reserved range
for unit length values. The issue was fixed in DWARF4.

Differential Revision: https://reviews.llvm.org/D64622

llvm-svn: 366190
2019-07-16 07:01:08 +00:00
Igor Kudrin
0b76a06c69 [DWARF] Fix an incorrect format specifier.
This adjusts the format specifier because PCOffset is uint16_t.

Differential Revision: https://reviews.llvm.org/D64620

llvm-svn: 366189
2019-07-16 06:56:10 +00:00
Igor Kudrin
3e859df823 [DWARF] Simplify DWARFAttribute. NFC.
The first argument in the constructor was ignored, and the remaining
arguments were always passed as their defaults.

Differential Revision: https://reviews.llvm.org/D64407

llvm-svn: 366188
2019-07-16 06:53:06 +00:00
Craig Topper
31bbc011c8 [X86] In combineStore, don't convert v2f32 load/store pairs to f64 loads/stores.
Type legalization can take care of this. This gives DAG combine
a little more time with the original types.

llvm-svn: 366182
2019-07-16 05:52:27 +00:00
Alex Bradbury
acb19e35a6 [RISCV] Match GNU tools canonical JALR and add aliases
The canonical GNU form of JALR resembles a load/store instruction rather
than placing the immediate offset as a separate argument, so match this
behaviour. Also add parser-only aliases for the three-operand form, and
add other shorter aliases also emitted by GNU tools.

Differential Revision: https://reviews.llvm.org/D55277
Patch by James Clarke.

llvm-svn: 366179
2019-07-16 04:56:43 +00:00
Rui Ueyama
1179e18f0c Fix parameter name comments using clang-tidy. NFC.
This patch applies clang-tidy's bugprone-argument-comment tool
to LLVM, clang and lld source trees. Here is how I created this
patch:

$ git clone https://github.com/llvm/llvm-project.git
$ cd llvm-project
$ mkdir build
$ cd build
$ cmake -GNinja -DCMAKE_BUILD_TYPE=Debug \
    -DLLVM_ENABLE_PROJECTS='clang;lld;clang-tools-extra' \
    -DCMAKE_EXPORT_COMPILE_COMMANDS=On -DLLVM_ENABLE_LLD=On \
    -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ ../llvm
$ ninja
$ parallel clang-tidy -checks='-*,bugprone-argument-comment' \
    -config='{CheckOptions: [{key: StrictMode, value: 1}]}' -fix \
    ::: ../llvm/lib/**/*.{cpp,h} ../clang/lib/**/*.{cpp,h} ../lld/**/*.{cpp,h}

llvm-svn: 366177
2019-07-16 04:46:31 +00:00
Alex Bradbury
d36e380c67 [RISCV] Avoid overflow when determining number of nops for code align
RISCVAsmBackend::shouldInsertExtraNopBytesForCodeAlign() assumed that the
align specified would be greater than or equal to the minimum nop length, but
that is not always the case - for example if a user specifies ".align 0" in
assembly.

Differential Revision: https://reviews.llvm.org/D63274
Patch by Edward Jones.

llvm-svn: 366176
2019-07-16 04:40:25 +00:00
Alex Bradbury
066798ae68 [RISCV] Fix a potential issue in shouldInsertFixupForCodeAlign()
The bool result of shouldInsertExtraNopBytesForCodeAlign() is not checked but
the returned nop count is unconditionally read even though it could be
uninitialized.

Differential Revision: https://reviews.llvm.org/D63285
Patch by Edward Jones.

llvm-svn: 366175
2019-07-16 04:37:19 +00:00
Alex Bradbury
8e05833474 [RISCV][NFC] Split PseudoCALL pattern out from instruction
Since PseudoCALL defines AsmString, it can be generated from assembly,
and so code-gen patterns should be defined separately to be consistent
with the style of the RISCV backend. Other pseudo-instructions exist
that have code-gen patterns defined directly, but these instructions are
purely for code-gen and cannot be written in assembly.

Differential Revision: https://reviews.llvm.org/D64012
Patch by James Clarke.

llvm-svn: 366174
2019-07-16 03:56:45 +00:00
Alex Bradbury
0ba2fb7efc [RISCV][NFC] Fix HasStedExtA -> HasStdExtA typo in comment
Differential Revision: https://reviews.llvm.org/D64011
Patch by James Clarke.

llvm-svn: 366173
2019-07-16 03:54:08 +00:00
Alex Bradbury
f609a0bd9b [RISCV] Make RISCVELFObjectWriter::getRelocType check IsPCRel
Previously, this function didn't check the IsPCRel argument. But doing so is a
useful check for errors, and also seemingly necessary for FK_Data_4 (which we
produce a R_RISCV_32_PCREL relocation for if IsPCRel).

Other than R_RISCV_32_PCREL, this should be NFC. Future exception handling
related patches will include tests that capture this behaviour.

llvm-svn: 366172
2019-07-16 03:47:34 +00:00
Peter Collingbourne
07693df04a hwasan: Pad arrays with non-1 size correctly.
Spotted by eugenis.

Differential Revision: https://reviews.llvm.org/D64783

llvm-svn: 366171
2019-07-16 03:25:50 +00:00
Matt Arsenault
b2782227ab AMDGPU: Avoid code predicates for extload PatFrags
Use the MemoryVT field. This will be necessary for tablegen to
automatically handle patterns for GlobalISel.

Doesn't handle the d16 lo/hi patterns. Those are a special case since
it involvess the custom node type.

llvm-svn: 366168
2019-07-16 02:46:05 +00:00
Jonas Devlieghere
e91ea804fa Re-land "[DebugInfo] Move function from line table to the prologue (NFC)"
In LLDB, when parsing type units, we don't need to parse the whole line
table. Instead, we only need to parse the "support files" from the line
table prologue.

To make that possible, this patch moves the respective functions from
the LineTable into the Prologue. Because I don't think users of the
LineTable should have to know that these files come from the Prologue,

I've left the original methods in place, and made them redirect to the
LineTable.

Differential revision: https://reviews.llvm.org/D64774

llvm-svn: 366164
2019-07-16 01:21:25 +00:00
Michael Liao
766f7435c5 [InstructionSimplify] Apply sext/trunc after pointer stripping
Summary:
- As the pointer stripping could trace through `addrspacecast` now, need
  to sext/trunc the offset to ensure it has the same width as the
  pointer after stripping.

Reviewers: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64768

llvm-svn: 366162
2019-07-16 01:03:06 +00:00
Jonas Devlieghere
3d2f6011b6 Revert "[DebugInfo] Move function from line table to the prologue (NFC)"
This broke LLD, which I didn't have enabled.

llvm-svn: 366160
2019-07-16 00:59:04 +00:00
Jonas Devlieghere
fe3b4f3f08 [DebugInfo] Move function from line table to the prologue (NFC)
In LLDB, when parsing type units, we don't need to parse the whole line
table. Instead, we only need to parse the "support files" from the line
table prologue.

To make that possible, this patch moves the respective functions from
the LineTable into the Prologue. Because I don't think users of the
LineTable should have to know that these files come from the Prologue,

I've left the original methods in place, and made them redirect to the
LineTable.

Differential revision: https://reviews.llvm.org/D64774

llvm-svn: 366158
2019-07-16 00:37:17 +00:00
Eric Christopher
249db97125 Temporarily Revert "[SLP] Recommit: Look-ahead operand reordering heuristic."
As there are some reported miscompiles with AVX512 and performance regressions
in Eigen. Verified with the original committer and testcases will be forthcoming.

This reverts commit r364964.

llvm-svn: 366154
2019-07-15 23:36:02 +00:00
Leonard Chan
d271428479 Revert "[NewPM] Port Sancov"
This reverts commit 5652f35817f07b16f8b3856d594cc42f4d7ee29c.

llvm-svn: 366153
2019-07-15 23:18:31 +00:00
Craig Topper
eb34bdf340 [X86] Teach convertToThreeAddress to handle SUB with immediate
We mostly avoid sub with immediate but there are a couple cases that can create them. One is the add 128, %rax -> sub -128, %rax trick in isel. The other is when a SUB immediate gets created for a compare where both the flags and the subtract value is used. If we are unable to linearize the SelectionDAG to satisfy the flag user and the sub result user from the same instruction, we will clone the sub immediate for the two uses. The one that produces flags will eventually become a compare. The other will have its flag output dead, and could then be considered for LEA creation.

I added additional test cases to add.ll to show the the sub -128 trick gets converted to LEA and a case where we don't need to convert it.

This showed up in the current codegen for PR42571.

Differential Revision: https://reviews.llvm.org/D64574

llvm-svn: 366151
2019-07-15 23:07:56 +00:00
Heejin Ahn
16f0f911f2 [WebAssembly] Add missing utility methods for exnref type
Summary:
This adds missing utility methods and copy instruction handling for
`exnref` type and also adds tests.

`tee` instruction tests are missing because `isTee` is currently only
used in ExplicitLocals pass and testing that pass in mir requires
serialization of stackified registers in mir files, which is a bit
nontrivial because `MachineFunctionInfo` only has info of vreg numbers
(which are large integers) but not the mir's register numbers. But this
change is quite trivial anyway.

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64705

llvm-svn: 366149
2019-07-15 23:04:00 +00:00
Yuanfang Chen
373457fb8b [llvm-readelf] Print "File: lib.a(file.o)" info when dumping archive files.
Match GNU readelf.

https://bugs.llvm.org/show_bug.cgi?id=35351

Reviewers: jhenderson, grimar, MaskRay, rupprecht

Reviewed by: jhenderson, MaskRay, grimar

Differential Revision: https://reviews.llvm.org/D64361

llvm-svn: 366147
2019-07-15 22:52:01 +00:00
Heejin Ahn
2b18b87f2b [WebAssembly] Rename except_ref type to exnref
Summary:
We agreed to rename `except_ref` to `exnref` for consistency with other
reference types in
https://github.com/WebAssembly/exception-handling/issues/79. This also
renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order
to use the file for other reference types in future.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64703

llvm-svn: 366145
2019-07-15 22:49:25 +00:00
Shoaib Meenai
3f57cf86fc Revert [llvm-lipo] Implement -create (with hardcoded alignments)
This reverts r366142 (git commit 67cee1dc7ee285b03372eb818a3894d35efa7394)

The test is failing on the Windows buildbots. Reverting while I
investigate.

llvm-svn: 366144
2019-07-15 22:44:08 +00:00
Shoaib Meenai
d3358a0215 [llvm-lipo] Implement -create (with hardcoded alignments)
Creates universal binary output file from input files. Currently uses
hard coded value for alignment.  Want to get the create functionality
approved before implementing the alignment function.

Patch by Anusha Basana <anusha.basana@gmail.com>

Differential Revision: https://reviews.llvm.org/D64102

llvm-svn: 366142
2019-07-15 22:29:30 +00:00
Heejin Ahn
8d13c8713f [WebAssembly] Simplify regcopy.mir
Summary:
This deletes the ll templates from the functions because they don't need
them (mir files need ll templates only when they have function calls or
BB names that are not numbers).

This also renames the filename to `reg-copy.mir`, because I'm planning
to add some more `reg-*.mir` soon.

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64704

llvm-svn: 366140
2019-07-15 22:22:10 +00:00
Wouter van Oortmerssen
f940c92ab2 [WebAssembly] Assembler: support special floats: infinity / nan
Summary:
These are emitted as identifiers by the InstPrinter, so we should
parse them as such. These could potentially clash with symbols of
the same name, but that is out of our (the WebAssembly backend) control.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64770

llvm-svn: 366139
2019-07-15 22:13:39 +00:00
Austin Kerbow
befddf9028 [AMDGPU] Enable merging m0 initializations.
Summary:
Enable hoisting and merging m0 defs that are initialized with the same
immediate value. Fixes bug where removed instructions are not considered
to interfere with other inits, and make sure to not hoist inits before block
prologues.

Reviewers: rampitec, arsenm

Reviewed By: rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64766

llvm-svn: 366135
2019-07-15 22:07:05 +00:00
Simon Atanasyan
73b9a74f3f [mips] Print BEQZL and BNEZL pseudo instructions
One of the reasons - to be compatible with GNU tools.

llvm-svn: 366133
2019-07-15 21:46:38 +00:00
Matt Arsenault
48d1562399 AMDGPU: Use standalone MUBUF load patterns
We already do this for the flat and DS instructions, although it is
certainly uglier and more verbose.

This will allow using separate pattern definitions for extload and
zextload. Currently we get away with using a single PatFrag with
custom predicate code to check if the extension type is a zextload or
anyextload. The generic mechanism the global isel emitter understands
treats these as mutually exclusive. I was considering making the
pattern emitter accept zextload or sextload extensions for anyextload
patterns, but in global isel, the different extending loads have
distinct opcodes, and there is currently no mechanism for an opcode
matcher to try multiple (and there probably is very little need for
one beyond this case).

llvm-svn: 366132
2019-07-15 21:41:44 +00:00
Nick Desaulniers
fe3275edf3 [LoopUnroll+LoopUnswitch] do not transform loops containing callbr
Summary:
There is currently a correctness issue when unrolling loops containing
callbr's where their indirect targets are being updated correctly to the
newly created labels, but their operands are not.  This manifests in
unrolled loops where the second and subsequent copies of callbr
instructions have blockaddresses of the label from the first instance of
the unrolled loop, which would result in nonsensical runtime control
flow.

For now, conservatively do not unroll the loop.  In the future, I think
we can pursue unrolling such loops provided we transform the cloned
callbr's operands correctly.

Such a transform and its legalities are being discussed in:
https://reviews.llvm.org/D64101

Link: https://bugs.llvm.org/show_bug.cgi?id=42489
Link: https://groups.google.com/forum/#!topic/clang-built-linux/z-hRWP9KqPI

Reviewers: fhahn, hfinkel, efriedma

Reviewed By: fhahn, hfinkel, efriedma

Subscribers: efriedma, hiraditya, zzheng, dmgreen, llvm-commits, pirama, kees, nathanchance, E5ten, craig.topper, chandlerc, glider, void, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64368

llvm-svn: 366130
2019-07-15 21:16:29 +00:00
Matt Arsenault
f6ccac1c17 TableGen/GlobalISel: Fix handling of truncstore patterns
This was failing to import the AMDGPU truncstore patterns. The
truncating stores from 32-bit to 8/16 were then somehow being
incorrectly selected to a 4-byte store.

A separate check is emitted for the LLT size in comparison to the
specific memory VT, which looks strange to me but makes sense based on
the hierarchy of PatFrags used for the default truncstore PatFrags.

llvm-svn: 366129
2019-07-15 21:15:20 +00:00
Matt Arsenault
100b40be1a TableGen: Add address space to matchers
Currently AMDGPU uses a CodePatPred to check address spaces from the
MachineMemOperand. Introduce a new first class property so that the
existing patterns can be easily modified to uses the new generated
predicate, which will also be handled for GlobalISel.

I would prefer these to match against the pointer type of the
instruction, but that would be difficult to get working with
SelectionDAG compatbility. This is much easier for now and will avoid
a painful tablegen rewrite for all the loads and stores.

I'm also not sure if there's a better way to encode multiple address
spaces in the table, rather than putting the number to expect.

llvm-svn: 366128
2019-07-15 20:59:42 +00:00
Matt Arsenault
efeedd6709 AMDGPU/GlobalISel: Allow scalar s1 and/or/xor
If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.

llvm-svn: 366125
2019-07-15 20:20:18 +00:00
Evgeniy Stepanov
e8363137ea ARM MTE stack sanitizer.
Add "memtag" sanitizer that detects and mitigates stack memory issues
using armv8.5 Memory Tagging Extension.

It is similar in principle to HWASan, which is a software implementation
of the same idea, but there are enough differencies to warrant a new
sanitizer type IMHO. It is also expected to have very different
performance properties.

The new sanitizer does not have a runtime library (it may grow one
later, along with a "debugging" mode). Similar to SafeStack and
StackProtector, the instrumentation pass (in a follow up change) will be
inserted in all cases, but will only affect functions marked with the
new sanitize_memtag attribute.

Reviewers: pcc, hctim, vitalybuka, ostannard

Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, steven_wu, dexonsmith, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D64169

llvm-svn: 366123
2019-07-15 20:02:23 +00:00