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6392 Commits

Author SHA1 Message Date
Jim Laskey
bc27bd0c6e Hopefully a good crack at making debugging work on intel -disable-fp-elim. 
llvm-svn: 31830
 2006-11-17 21:19:15 +00:00
Jim Laskey
a1f032c03a Assert unhandled case. 
llvm-svn: 31828
 2006-11-17 18:49:39 +00:00
Jim Laskey
b56f73f709 1. Ignore the -disable-fp-elim when the routine is a leaf. 
2. Offsets on 64-bit stores are still in bytes.

llvm-svn: 31824
 2006-11-17 16:09:31 +00:00
Jim Laskey
e0ff7bdbd3 Typo. Fix the nightly tests. 
llvm-svn: 31823
 2006-11-17 14:06:41 +00:00
Bill Wendling
b6061e32fa Removed even more std::cerr and #include <iostream> things. 
llvm-svn: 31813
 2006-11-17 07:52:03 +00:00
Chris Lattner
81683aa08b implement a todo: change a map into a vector 
llvm-svn: 31805
 2006-11-17 01:52:23 +00:00
Chris Lattner
e4e113818f fix typo 
llvm-svn: 31799
 2006-11-17 00:49:36 +00:00
Chris Lattner
237ee79d06 implicit_def_vrrc doesn't generate code. 
llvm-svn: 31797
 2006-11-16 23:49:52 +00:00
Evan Cheng
fc1b3d8bc8 Correct instructions for moving data between GR64 and SSE registers; also correct load i64 / store i64 from v2i64. 
llvm-svn: 31795
 2006-11-16 23:33:25 +00:00
Evan Cheng
a838021d2c Fix a potential bug: MOVPDI2DI, etc. are not copy instructions. 
llvm-svn: 31794
 2006-11-16 23:22:26 +00:00
Jim Laskey
8aac7dc0ee This is a general clean up of the PowerPC ABI. Address several problems and 
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.

llvm-svn: 31792
 2006-11-16 22:43:37 +00:00
Chris Lattner
5dcf43138d fix a regression that I introduced. stdu should scale the offset by 4 
before printing it.

llvm-svn: 31791
 2006-11-16 21:45:30 +00:00
Evan Cheng
c653e70b2d Align stubs on 4 byte boundary. This fixes 447.dealII. 
llvm-svn: 31790
 2006-11-16 20:13:34 +00:00
Chris Lattner
41280ae60d add a statistic 
llvm-svn: 31785
 2006-11-16 18:13:49 +00:00
Chris Lattner
283e7306c1 fix broken encoding 
llvm-svn: 31778
 2006-11-16 01:01:28 +00:00
Chris Lattner
99d9dd8d07 add ppc64 r+i stores with update. 
llvm-svn: 31776
 2006-11-16 00:57:19 +00:00
Chris Lattner
4edb6f09fe add patterns for ppc32 preinc stores. ppc64 next. 
llvm-svn: 31775
 2006-11-16 00:41:37 +00:00
Chris Lattner
c4b9cff1f9 switch these back to the 'bad old way' 
llvm-svn: 31774
 2006-11-16 00:33:34 +00:00
Chris Lattner
f505815dad Fix ppc64 epilog bug. 
llvm-svn: 31771
 2006-11-15 23:35:30 +00:00
Chris Lattner
bd95b9d4ae Stop using isTwoAddress, switching to operand constraints instead. 
Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).

llvm-svn: 31770
 2006-11-15 23:24:18 +00:00
Chris Lattner
1158705ea7 add a new field needed by the code emitter generator. 
llvm-svn: 31768
 2006-11-15 22:55:04 +00:00
Evan Cheng
2a92afa25d Properly transfer kill / dead info. 
llvm-svn: 31765
 2006-11-15 20:58:11 +00:00
Evan Cheng
1b3bde1c1b Kill / dead info has been moved to MI's. 
llvm-svn: 31764
 2006-11-15 20:56:39 +00:00
Evan Cheng
4625504fa4 commuteInstruction should propagate kill / dead info. 
llvm-svn: 31763
 2006-11-15 20:56:03 +00:00
Chris Lattner
9bc55a6c38 fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri 
addrmodes.

llvm-svn: 31757
 2006-11-15 19:55:13 +00:00
Chris Lattner
ccbbe940eb Simplify IntrinsicLowering and clarify that it is only for use by the 
CBE and interpreter.

llvm-svn: 31755
 2006-11-15 18:00:10 +00:00
Chris Lattner
1453db28c3 Remove unneeded forward decls 
llvm-svn: 31754
 2006-11-15 17:53:13 +00:00
Chris Lattner
2f520b36ba Fix the PPC regressions last night 
llvm-svn: 31752
 2006-11-15 17:40:51 +00:00
Chris Lattner
6d5a509e34 Switch loads over to use memri as the operand instead of a reg/imm operand 
pair for cleanliness.  Add instructions for PPC32 preinc-stores with commented
out patterns.  More improvement is needed to enable the patterns, but we're
getting close.

llvm-svn: 31749
 2006-11-15 02:43:19 +00:00
Evan Cheng
7c9b3c7ea3 Revert. This wasn't meant to be checked in. 
llvm-svn: 31737
 2006-11-14 19:20:33 +00:00
Chris Lattner
55c68f61a7 group load and store instructions together. No functionality change. 
llvm-svn: 31736
 2006-11-14 19:19:53 +00:00
Chris Lattner
6c55120e31 Fix predicates for unindexed stores so they don't accidentally match indexed 
stores.

llvm-svn: 31735
 2006-11-14 19:13:39 +00:00
Chris Lattner
dc48b6a77c Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls 
clobber.  This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity.  This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.

llvm-svn: 31734
 2006-11-14 18:44:47 +00:00
Chris Lattner
10b528d5c3 remove a ton of custom selection logic no longer needed 
llvm-svn: 31733
 2006-11-14 18:43:11 +00:00
Chris Lattner
da103686a6 it would be nice of ctlz were lowered to bsf etc. 
llvm-svn: 31730
 2006-11-14 08:08:46 +00:00
Chris Lattner
e3a81b796c lower "X = seteq Y, Z" to '(shr (ctlz (xor Y, Z)), 5)' instead of 
'(shr (ctlz (sub Y, Z)), 5)'.

The use of xor better exposes the operation to bit-twiddling logic in the
dag combiner.  For example, this:

typedef struct {
  unsigned prefix : 4;
  unsigned code : 4;
  unsigned unsigned_p : 4;
} tree_common;

int foo(tree_common *a, tree_common *b) {
  return a->code == b->code;
}

Now compiles to:

_foo:
        lwz r2, 0(r4)
        lwz r3, 0(r3)
        xor r2, r3, r2
        rlwinm r2, r2, 28, 28, 31
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

instead of:

_foo:
        lbz r2, 3(r4)
        lbz r3, 3(r3)
        srwi r2, r2, 4
        srwi r3, r3, 4
        subf r2, r2, r3
        cntlzw r2, r2
        srwi r3, r2, 5
        blr

saving a cycle.

llvm-svn: 31725
 2006-11-14 05:28:08 +00:00
Chris Lattner
8913d79def add a note 
llvm-svn: 31719
 2006-11-14 01:57:53 +00:00
Chris Lattner
fdffc51d57 minor tweaks, reject vector preinc. 
llvm-svn: 31717
 2006-11-14 01:38:31 +00:00
Evan Cheng
0e82270ff2 Matches MachineInstr changes. 
llvm-svn: 31712
 2006-11-13 23:36:35 +00:00
Chris Lattner
81ea2c7c0a teach the g5 hazard recognizer about update loads. This fixes 
Ptrdist/anagram among others.

llvm-svn: 31708
 2006-11-13 20:11:06 +00:00
Nick Lewycky
f4f28f415d Cute example from Chris Lattner. 
llvm-svn: 31696
 2006-11-13 00:23:28 +00:00
Jim Laskey
d692c1a0ab Make sure stack link is set in 64-bit. 
llvm-svn: 31690
 2006-11-11 22:22:07 +00:00
Chris Lattner
b5aefe29ae implement proper PPC64 prolog/epilog codegen. 
llvm-svn: 31684
 2006-11-11 19:05:28 +00:00
Jim Laskey
f5bffa5670 Running with frame pointers prevented debugging, external probes and 
potentially some system calls/exception handling from working.  TOS must always
link to previous frame.  This is a short term workaround until alloca scheme is
reworked.

llvm-svn: 31677
 2006-11-11 10:21:58 +00:00
Evan Cheng
b9e2ae9e37 Add implicit use / def operands to created MI's. 
llvm-svn: 31676
 2006-11-11 10:21:44 +00:00
Evan Cheng
f880ed86ff Add all implicit defs to FP_REG_KILL mi. 
llvm-svn: 31674
 2006-11-11 07:19:36 +00:00
Chris Lattner
1409347c13 allow the offset of a preinc'd load to be the low-part of a global. This 
produces this clever code:

_millisecs:
        lis r2, ha16(_Time.1182)
        lwzu r3, lo16(_Time.1182)(r2)
        lwz r2, 4(r2)
        addic r4, r2, 1
        addze r3, r3
        blr

instead of this:

_millisecs:
        lis r2, ha16(_Time.1182)
        la r3, lo16(_Time.1182)(r2)
        lwz r2, lo16(_Time.1182)(r2)
        lwz r3, 4(r3)
        addic r4, r3, 1
        addze r3, r2
        blr

for:

long %millisecs() {
        %tmp = load long* %Time.1182            ; <long> [#uses=1]
        %tmp1 = add long %tmp, 1                ; <long> [#uses=1]
        ret long %tmp1
}

llvm-svn: 31673
 2006-11-11 04:53:30 +00:00
Chris Lattner
3d48461071 Mark operands as symbol lo instead of imm32 so that they print lo(x) around 
globals.

llvm-svn: 31672
 2006-11-11 04:51:36 +00:00
Chris Lattner
9c5d395b0e ppc64 doesn't have lwau, don't attempt to form it. 
llvm-svn: 31656
 2006-11-11 00:08:42 +00:00
Chris Lattner
1aaa5f904c implement preinc support for r+i loads on ppc64 
llvm-svn: 31654
 2006-11-10 23:58:45 +00:00