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Author SHA1 Message Date
Chris Lattner
e7ce5d0e4c Add missing entry. 
llvm-svn: 19712
 2005-01-20 17:32:28 +00:00
Chris Lattner
8b0a2a3251 Fix a crash compiling 134.perl. 
llvm-svn: 19711
 2005-01-20 16:50:16 +00:00
Jeff Cohen
72f52d5277 Get analyze to show all analysis options when compiled with VC++ 
llvm-svn: 19710
 2005-01-20 05:19:40 +00:00
Jeff Cohen
be9072767e Add analyze project to Visual Studio 
llvm-svn: 19709
 2005-01-20 04:52:59 +00:00
Jeff Cohen
21ccf213ed Add project llvm-proj to Visual Studio 
llvm-svn: 19708
 2005-01-20 04:41:49 +00:00
Chris Lattner
e5212a16a2 Support targets that do not use i8 shift amounts. 
llvm-svn: 19707
 2005-01-19 22:31:21 +00:00
Chris Lattner
5a9660aa71 Add two optimizations. The first folds (X+Y)-X -> Y 
The second folds operations into selects, e.g. (select C, (X+Y), (Y+Z))
-> (Y+(select C, X, Z)

This occurs a few times across spec, e.g.

         select    add/sub
mesa:    83        0
povray:  5         2
gcc      4         2
parser   0         22
perlbmk  13        30
twolf    0         3

llvm-svn: 19706
 2005-01-19 21:50:18 +00:00
Chris Lattner
f9b2da8e63 Add some new tests 
llvm-svn: 19705
 2005-01-19 21:48:31 +00:00
Chris Lattner
0e7435bc5b Add an assertion that would have made more sense to duraid 
llvm-svn: 19704
 2005-01-19 21:32:07 +00:00
Chris Lattner
c662697319 Add support for targets that pass args in registers to calls. 
llvm-svn: 19703
 2005-01-19 20:24:35 +00:00
Chris Lattner
7005632b59 Add an accessor for targets that pass args in regs 
llvm-svn: 19702
 2005-01-19 20:19:58 +00:00
Chris Lattner
277ac2be70 Fold single use token factor nodes into other token factor nodes. 
llvm-svn: 19701
 2005-01-19 19:10:54 +00:00
Chris Lattner
85e0771f79 Realize the individual pieces of an expanded copytoreg/store/load are 
independent of each other.

llvm-svn: 19700
 2005-01-19 18:02:17 +00:00
Chris Lattner
027c97e93e Know some identities about tokenfactor nodes. 
llvm-svn: 19699
 2005-01-19 18:01:40 +00:00
Chris Lattner
7114e8a527 Know some simple identities. This improves codegen for (1LL << N). 
llvm-svn: 19698
 2005-01-19 17:29:49 +00:00
Chris Lattner
6534e1ede3 Fix a problem where were were literally selecting for INCREASED register 
pressure, not decreases register pressure.  Fix problem where we accidentally
swapped the operands of SHLD, which caused fourinarow to fail.  This fixes
fourinarow.

llvm-svn: 19697
 2005-01-19 17:24:34 +00:00
Chris Lattner
e97ed92617 Just in case, handle something that is both a use and a def. 
llvm-svn: 19696
 2005-01-19 17:11:51 +00:00
Chris Lattner
2cb11bd2b9 When an instruction moves, make sure to update the VarInfo::Kills list as 
well as all of teh other stuff in livevar. This fixes the compiler crash
on fourinarow last night.

llvm-svn: 19695
 2005-01-19 17:09:15 +00:00
Chris Lattner
b75589131d When commuting these instructions, make sure to actually swap the operands too. 
llvm-svn: 19694
 2005-01-19 16:55:52 +00:00
Chris Lattner
302ea8908d Fix 'raise' to work with packed types. Patch by Morten Ofstad. 
llvm-svn: 19693
 2005-01-19 16:16:35 +00:00
Chris Lattner
fde1a5688b Implement Regression/CodeGen/X86/rotate.ll: emit rotate instructions (which 
typically cost 1 cycle) instead of shld/shrd instruction (which are typically
6 or more cycles).  This also saves code space.

For example, instead of emitting:

rotr:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %CL, BYTE PTR [%ESP + 8]
        shrd %EAX, %EAX, %CL
        ret
rotli:
        mov %EAX, DWORD PTR [%ESP + 4]
        shrd %EAX, %EAX, 27
        ret

Emit:

rotr32:
        mov %CL, BYTE PTR [%ESP + 8]
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, %CL
        ret
rotli32:
        mov %EAX, DWORD PTR [%ESP + 4]
        ror %EAX, 27
        ret

We also emit byte rotate instructions which do not have a sh[lr]d counterpart
at all.

llvm-svn: 19692
 2005-01-19 08:07:05 +00:00
Chris Lattner
bde28b8ebe New testcase for rotate instructions. Each function should codegen to a 
rotate.

llvm-svn: 19691
 2005-01-19 08:04:08 +00:00
Chris Lattner
34757ff939 Add rotate instructions. 
llvm-svn: 19690
 2005-01-19 07:50:03 +00:00
Chris Lattner
e539ce8223 Match 16-bit shld/shrd instructions as well, implementing shift-double.llx:test5 
llvm-svn: 19689
 2005-01-19 07:37:26 +00:00
Chris Lattner
33f679dba9 Add a test for 16-bit sh*d. 
llvm-svn: 19688
 2005-01-19 07:37:01 +00:00
Chris Lattner
9d5ee289d7 Improve coverage of the X86 instruction set by adding 16-bit shift doubles. 
llvm-svn: 19687
 2005-01-19 07:31:24 +00:00
Chris Lattner
c03f360215 Teach the code generator that shrd/shld is commutable if it has an immediate. 
This allows us to generate this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shld %EDX, %EDX, 2
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
        mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

Note the magically transmogrifying immediate.

llvm-svn: 19686
 2005-01-19 07:11:01 +00:00
Chris Lattner
408325ffdf Use the TargetInstrInfo::commuteInstruction method to commute instructions 
instead of doing it manually.

llvm-svn: 19685
 2005-01-19 07:08:42 +00:00
Chris Lattner
33efebcdc8 Finegrainify namespacification 
Add default impl of commuteInstruction
Add notes about ugly V9 code.

llvm-svn: 19684
 2005-01-19 06:53:34 +00:00
Chris Lattner
2a03fa3a5c Add a new method, described in the comment. 
llvm-svn: 19683
 2005-01-19 06:53:02 +00:00
Chris Lattner
ceca0b7b62 Ensure that each these functions generates a sh[rl]d instruction. 
llvm-svn: 19682
 2005-01-19 06:30:36 +00:00
Chris Lattner
575e912fcf Codegen long >> 2 to this: 
foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %EDX, DWORD PTR [%ESP + 8]
        shrd %EAX, %EDX, 2
        sar %EDX, 2
        ret

instead of this:

test1:
        mov %ECX, DWORD PTR [%ESP + 4]
        shr %ECX, 2
        mov %EDX, DWORD PTR [%ESP + 8]
        mov %EAX, %EDX
        shl %EAX, 30
        or %EAX, %ECX
        sar %EDX, 2
        ret

and long << 2 to this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, DWORD PTR [%ESP + 8]
***     mov %EDX, %EAX
        shrd %EDX, %ECX, 30
        shl %EAX, 2
        ret

instead of this:

foo:
        mov %EAX, DWORD PTR [%ESP + 4]
        mov %ECX, %EAX
        shr %ECX, 30
        mov %EDX, DWORD PTR [%ESP + 8]
        shl %EDX, 2
        or %EDX, %ECX
        shl %EAX, 2
        ret

The extra copy (marked ***) can be eliminated when I teach the code generator
that shrd32rri8 is really commutative.

llvm-svn: 19681
 2005-01-19 06:18:43 +00:00
Jeff Cohen
a3414ac8c7 Add missing data types for VC++ 
llvm-svn: 19680
 2005-01-19 05:08:31 +00:00
Chris Lattner
743a36c818 Implement a way of expanding shifts. This applies to targets that offer 
select operations or to shifts that are by a constant.  This automatically
implements (with no special code) all of the special cases for shift by 32,
shift by < 32 and shift by > 32.

llvm-svn: 19679
 2005-01-19 04:19:40 +00:00
Chris Lattner
419a5d213b X86 shifts mask the amount. 
llvm-svn: 19678
 2005-01-19 03:36:30 +00:00
Chris Lattner
fbd1f8e4fd Add a hook to find out how the target handles shift amounts that are out of 
range.  Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).

This defaults to undefined, which is conservatively correct.

llvm-svn: 19677
 2005-01-19 03:36:14 +00:00
Chris Lattner
4938a7c8a1 Move all data members to the end of the class. 
Add a hook to find out how the target handles shift amounts that are out of
range.  Either they are undefined (the default), they mask the shift amount
to the size of the register (X86, Alpha, etc), or they extend the shift (PPC).

This defaults to undefined, which is conservatively correct.

llvm-svn: 19676
 2005-01-19 03:36:03 +00:00
Chris Lattner
0df1935505 Zero is cheaper than sign extend. 
llvm-svn: 19675
 2005-01-18 21:57:59 +00:00
Chris Lattner
6dec8cb829 Code to handle FP_EXTEND is dead now. X86 doesn't support any data types to 
FP_EXTEND from!

llvm-svn: 19674
 2005-01-18 20:05:56 +00:00
Chris Lattner
798e9c85d6 Remove more dead code. 
llvm-svn: 19673
 2005-01-18 19:50:08 +00:00
Chris Lattner
401814508f The selection dag code handles the promotions from F32 to F64 for us, so we 
don't need to even think about F32 in the X86 code anymore.

llvm-svn: 19672
 2005-01-18 19:46:54 +00:00
Chris Lattner
4360871e16 Fix some fixmes (promoting bools for select and brcond), fix promotion 
of zero and sign extends.

llvm-svn: 19671
 2005-01-18 19:27:06 +00:00
Chris Lattner
eea485de1f Keep track of the retval type as well. 
llvm-svn: 19670
 2005-01-18 19:26:36 +00:00
Chris Lattner
0697def39d Keep track of the returned value type as well. 
llvm-svn: 19669
 2005-01-18 19:26:18 +00:00
Chris Lattner
ff086f3016 Teach legalize to promote copy(from|to)reg, instead of making the isel pass 
do it.  This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.

llvm-svn: 19668
 2005-01-18 17:54:55 +00:00
Chris Lattner
dc09e52b3e Fix 124.m88ksim. 
llvm-svn: 19667
 2005-01-18 17:35:28 +00:00
Jeff Cohen
d991f0c15f Add project llvm-ld to Visual Studio 
llvm-svn: 19665
 2005-01-18 05:44:50 +00:00
Jeff Cohen
01ca103f97 Add project llvm-nm to Visual Studio 
llvm-svn: 19664
 2005-01-18 05:44:25 +00:00
Jeff Cohen
7c05504d8d Add project llvm-ld to Visual Studio 
llvm-svn: 19663
 2005-01-18 05:39:37 +00:00
Jeff Cohen
d07f37da2e Add llvm-bcanalyzer project to Visual Studio 
llvm-svn: 19662
 2005-01-18 05:31:34 +00:00