Commit Graph

122969 Commits

Author SHA1 Message Date
Alexey Samsonov
e8d7a2ffd9 Move parts of llvm-symbolizer tool into LLVMSymbolize library.
Summary: See http://lists.llvm.org/pipermail/llvm-dev/2015-October/091624.html

Reviewers: echristo

Subscribers: llvm-commits, aizatsky

Differential Revision: http://reviews.llvm.org/D13998

llvm-svn: 251316
2015-10-26 17:56:12 +00:00
Jonas Paulsson
38d806f873 [SystemZ] LTGFR use regclass should be GR32, not GR64.
Discovered by testing int-cmp-44.ll with -verify-machineinstrs (added to
test run).

llvm-svn: 251299
2015-10-26 15:03:49 +00:00
Jonas Paulsson
5395a3ead2 [SystemZ] Also clear kill flag for index reg in splitMove().
Discovered by running fp-move-05.ll with -verify-machineinstrs (added
to test case run).

llvm-svn: 251298
2015-10-26 15:03:41 +00:00
Jonas Paulsson
16285ec728 [SystemZ] Don't forget the CC def op on LTEBRCompare pseudos
Discovered by running fp-cmp-02.ll with -verify-machineinstrs (now added
to test run).

llvm-svn: 251297
2015-10-26 15:03:32 +00:00
Jonas Paulsson
655a8ff4b6 [SystemZ] Tie operands in SystemZShorteInst if MI becomes 2-address.
Discovered by testing fp-add-02.ll with -verify-machineinstrs.

Test case updated to always run with -verify-machineinstrs.

llvm-svn: 251296
2015-10-26 15:03:07 +00:00
Vasileios Kalintiris
6fab073b1a [mips] Check for the correct error message in tests for interrupt attributes.
Instead of XFAIL-ing the tests with the wrong usage of the "interrupt"
attribute, we should check that we emit the correct error messages to
the user.

llvm-svn: 251295
2015-10-26 14:24:30 +00:00
James Molloy
8d9daddc1b [ValueTracking] Extend r251146 to catch a fairly common case
Even though we may not know the value of the shifter operand, it's possible we know the shifter operand is non-zero. This can allow us to infer more known bits - for example:

  %1 = load %p !range {1, 5}
  %2 = shl %q, %1

We don't know %1, but we do know that it is nonzero so %2[0] is known zero, and importantly %2 is known non-zero.

Calling isKnownNonZero is nontrivially expensive so use an Optional to run it lazily and cache its result.

llvm-svn: 251294
2015-10-26 14:10:46 +00:00
Silviu Baranga
6912e3b382 [SCEV] Fix issues found during the review of r251283. NFC.
Summary:
Replace (const SCEVAddRecExpr *) with cast<SCEVAddRecExpr>.

Rename SCEVApplyRewriter to SCEVLoopAddRecRewriter (which is a more
appropriate name) since the description is "takes a scalar evolution
expression and applies the Map (Loop -> SCEV) to all AddRecExprs."

Subscribers: llvm-commits, sanjoy

Differential Revision: http://reviews.llvm.org/D14065

llvm-svn: 251292
2015-10-26 13:50:06 +00:00
Elena Demikhovsky
5e7ce7f64e Loop Vectorizer - skipping "bitcast" before GEP
Vectorization of memory instruction (Load/Store) is possible when the pointer is coming from GEP. The GEP analysis allows to estimate the profit.
In some cases we have a "bitcast" between GEP and memory instruction.
I added code that skips the "bitcast".

http://reviews.llvm.org/D13886

llvm-svn: 251291
2015-10-26 13:42:41 +00:00
Tim Northover
2b47a04ccd Tests: be slightly more specific to avoid conflict with path.
llvm-svn: 251290
2015-10-26 13:40:03 +00:00
Igor Breger
0ec388e259 fix test errors (on windows) for commit r251287
llvm-svn: 251288
2015-10-26 13:31:41 +00:00
Igor Breger
0803d66832 AVX512: Enabled VPBROADCASTB lowering for v64i8 vectors.
Differential Revision: http://reviews.llvm.org/D13896

llvm-svn: 251287
2015-10-26 13:01:02 +00:00
Vasileios Kalintiris
4ad8f46d36 [mips] Interrupt attribute support for mips32r2+.
Summary:
This patch adds support for using the "interrupt" attribute on Mips
for interrupt handling functions. At this time only mips32r2+ with the
o32 ABI with the static relocation model is supported. Unsupported
configurations will be rejected

Patch by Simon Dardis (+ clang-format & some trivial changes to follow the
LLVM coding standards by me).

Reviewers: mpf, dsanders

Subscribers: dsanders, vkalintiris, llvm-commits

Differential Revision: http://reviews.llvm.org/D10768

llvm-svn: 251286
2015-10-26 12:38:43 +00:00
Igor Breger
1ab3a1be2f AVX-512: Use correct extract vector length.
Bug https://llvm.org/bugs/show_bug.cgi?id=25318

Differential Revision: http://reviews.llvm.org/D14062

llvm-svn: 251285
2015-10-26 12:26:34 +00:00
Silviu Baranga
475ca33ce8 [SCEV] Factor out common visiting patterns for SCEV rewriters. NFC.
Summary:
Add a SCEVRewriteVisitor class which contains the common
visiting patterns used when rewriting SCEVs.

SCEVParameterRewriter and SCEVApplyRewriter now inherit
from SCEVRewriteVisitor (and are therefore much simpler).

Reviewers: anemet, mzolotukhin, sanjoy

Subscribers: rengolin, llvm-commits, sanjoy

Differential Revision: http://reviews.llvm.org/D13242

llvm-svn: 251283
2015-10-26 11:18:31 +00:00
Silviu Baranga
8fa79f5d2b [InstCombine] Teach instcombine not to create extra PHI nodes when folding GEPs
Summary:
InstCombine tries to transform GEP(PHI(GEP1, GEP2, ..)) into GEP(GEP(PHI(...))
when possible. However, this may leave the old PHI node around. Even if we
do end up folding the GEPs, having an extra PHI node might not be beneficial.

This change makes the transformation more conservative. We now only do this if
the PHI has only one use, and can therefore be removed after the transformation.

Reviewers: jmolloy, majnemer

Subscribers: mcrosier, mssimpso, llvm-commits

Differential Revision: http://reviews.llvm.org/D13887

llvm-svn: 251281
2015-10-26 10:25:05 +00:00
James Molloy
61f60676db [ARM] Handle the inline asm constraint type 'o'
This means "memory with offset" and requires very little plumbing to get working. This fixes PR25317.

llvm-svn: 251280
2015-10-26 10:04:52 +00:00
Benjamin Kramer
3880607b0c Drop code after unreachable. No functionality change.
llvm-svn: 251278
2015-10-26 09:55:45 +00:00
Igor Breger
d41ad7cd99 AVX512: Add AVX-512 not materializable instructions.
Otherwise value can be reused , despite its value could be changed - produces incorrect assembler.

https://llvm.org/bugs/show_bug.cgi?id=25270

Differential Revision: http://reviews.llvm.org/D14057

llvm-svn: 251275
2015-10-26 08:37:12 +00:00
Lang Hames
6c8099881d [Orc] Add license header to OrcTargetSupport.
llvm-svn: 251274
2015-10-26 06:40:28 +00:00
Lang Hames
7084a1b83c [Orc] In the CompileOnDemand layer, wrap module ownership in order to preserve
the module pointer type passed in by the user.

The previous ownership scheme, where the user pointer was always moved into a
std::shared_ptr, breaks if the user passes in a raw pointer.

Discovered while working on the Orc C API, which should be landing shortly.
I expect to include a test-case with that.

llvm-svn: 251273
2015-10-26 06:37:04 +00:00
David Majnemer
4569f65398 Update test to take into account for r251271.
llvm-svn: 251272
2015-10-26 03:34:29 +00:00
David Majnemer
0e608b0bdb [MC] Add support for GNU as-compatible binary operator precedence
GNU as and Darwin give the various binary operators different
precedence.  LLVM's MC supported the Darwin semantics but not the GNU
semantics.

This fixes PR25311.

llvm-svn: 251271
2015-10-26 03:15:34 +00:00
David Majnemer
296cfbf069 [MC] Don't crash when .word is given bogus values
We didn't validate that the .word directive was given a sane value,
leading to crashes when we attempt to write out the object file.

Instead, perform some validation and issue a diagnostic pointing at the
start of the diagnostic.

llvm-svn: 251270
2015-10-26 02:45:50 +00:00
Tobias Grosser
1d63bd132d RegionInfo: Correctly expand regions
Instead of playing around with dominance to verify if the possible expansion of
a scop region is indeed a single entry single exit region, we now distinguish
two cases. In case we only append a basic block, all edges entering this basic
block need to have come from within the region that is expanded. In case we join
two regions, the source basic blocks of the edges that end at the entry node of
the region that is appended most be part of either the original region or the
region that is appended.

This change will be tested through Polly.

This fixes llvm.org/PR25242

llvm-svn: 251267
2015-10-25 22:55:59 +00:00
Benjamin Kramer
2c2eefe199 Convert assert(false) into llvm_unreachable where it makes sense.
llvm-svn: 251266
2015-10-25 22:28:27 +00:00
Simon Pilgrim
737e959265 [X86][AVX] Regenerate tests.
llvm-svn: 251263
2015-10-25 21:47:09 +00:00
Saleem Abdulrasool
2d3fcc35ee docs: document x mangling in LangRef
Windows has two different mangling specifiers.  `x` is used on x86 for the `_`
UserLabelPrefix.  Others use `w` for the no UserLabelPrefix.

llvm-svn: 251260
2015-10-25 20:39:35 +00:00
Davide Italiano
6406920ed6 [ScalarEvolution] Throw away dead code.
llvm-svn: 251256
2015-10-25 20:00:49 +00:00
Davide Italiano
0d0d89527e [ScalarEvolution] Get rid of NDEBUG in header (correctly this time).
llvm-svn: 251255
2015-10-25 19:55:24 +00:00
Sanjoy Das
ef521e177e [LCSSA] Unbreak build, don't reuse L; NFC
The build broke in r251248.

llvm-svn: 251251
2015-10-25 19:27:17 +00:00
Davide Italiano
ee0fec74a3 [ScalarEvolution] Get rid of NDEBUG in header.
llvm-svn: 251249
2015-10-25 19:13:36 +00:00
Sanjoy Das
d668744358 [LCSSA] Use range for loops; NFC
llvm-svn: 251248
2015-10-25 19:08:32 +00:00
Simon Pilgrim
8a425d054a [X86][SSE4A] Fix for EXTRQI shuffle lowering.
Incorrect range test - found during fuzz testing.

llvm-svn: 251245
2015-10-25 17:40:54 +00:00
Simon Pilgrim
9f524cbd0e [X86][SSE] Refreshed tests (missing AVX512 patterns)
llvm-svn: 251238
2015-10-25 15:39:22 +00:00
Elena Demikhovsky
b4a97e3e11 Scalarizer for masked.gather and masked.scatter intrinsics.
When the target does not support these intrinsics they should be converted to a chain of scalar load or store operations.
If the mask is not constant, the scalarizer will build a chain of conditional basic blocks.
I added isLegalMaskedGather() isLegalMaskedScatter() APIs.

Differential Revision: http://reviews.llvm.org/D13722

llvm-svn: 251237
2015-10-25 15:37:55 +00:00
Simon Pilgrim
38248c9e16 [X86][SSE] Added tests for shuffling through bitcasts.
llvm-svn: 251236
2015-10-25 15:32:04 +00:00
Simon Pilgrim
e62b3606fd [X86][SSE] vector sext/zext tests - remove unnecessary mcpu arguments
llvm-svn: 251233
2015-10-25 12:15:00 +00:00
Simon Pilgrim
192a1a80e3 [X86][SSE] shift/rotate tests - remove unnecessary mcpu arguments and regenerate/cleanup
llvm-svn: 251232
2015-10-25 12:07:45 +00:00
Simon Pilgrim
70364eb5c0 [X86] PMOV*X* tests - remove unnecessary mcpu arguments and regenerate
llvm-svn: 251230
2015-10-25 11:55:10 +00:00
Simon Pilgrim
eeb5ceae70 [X86] Stack folding tests - just use mtriple - no need for mcpu in these tests
llvm-svn: 251229
2015-10-25 11:42:46 +00:00
Michael Kuperstein
b8a24f50b1 [X86] Use correct calling convention for MCU psABI libcalls
When using the MCU psABI, compiler-generated library calls should pass
some parameters in-register. However, since inreg marking for x86 is currently
done by the front end, it will not be applied to backend-generated calls.

This is a workaround for PR3997, which describes a similar issue for -mregparm.

Differential Revision: http://reviews.llvm.org/D13977

llvm-svn: 251223
2015-10-25 08:14:05 +00:00
Michael Kuperstein
f5ce8355a3 [X86] Add support for elfiamcu triple
This adds support for the i?86-*-elfiamcu triple, which indicates the IAMCU psABI is used.

Differential Revision: http://reviews.llvm.org/D13977

llvm-svn: 251222
2015-10-25 08:07:37 +00:00
Craig Topper
53b91789eb Remove two unnecessary conversions from MVT to EVT. NFC
llvm-svn: 251219
2015-10-25 03:15:29 +00:00
Craig Topper
52507d4b85 Use MVT::SimpleValueType instead of MVT in template parameter. NFC
llvm-svn: 251217
2015-10-25 00:27:14 +00:00
Rafael Espindola
16110f1617 Simplify boolean conditional return statements in tools/llvm-symbolizer.
Patch by Richard.

llvm-svn: 251216
2015-10-24 23:23:25 +00:00
Rafael Espindola
1149216eae Simplify boolean expressions in tools/llvm-objdump.
Patch by Richard.

llvm-svn: 251215
2015-10-24 23:19:10 +00:00
Rafael Espindola
4f88a5b854 Refactor: Simplify boolean conditional return statements in lib/CodeGen.
Patch by Richard.

llvm-svn: 251213
2015-10-24 23:11:13 +00:00
Simon Pilgrim
667daf3b66 [X86][SSE] Use lowerVectorShuffleWithUNPCK instead of custom matches.
Most 128-bit and 256-bit shuffles were manually matching UNPCK patterns - use lowerVectorShuffleWithUNPCK to be more thorough.

llvm-svn: 251211
2015-10-24 22:45:04 +00:00
Davide Italiano
59b56f0a89 [Support] Add comment to explain why we can't drop NDEBUG.
Discussed with: Benjamin Kramer.

llvm-svn: 251210
2015-10-24 22:15:32 +00:00