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21285 Commits

Author SHA1 Message Date
Akira Hatanaka
574e68feec Add another peephole pattern for conditional moves. 
llvm-svn: 156460
 2012-05-09 02:29:29 +00:00
Jakob Stoklund Olesen
88cf278739 Use ptr_rc_tailcall instead of GR32_TC. 
The getPointerRegClass() hook will return GR32_TC, or whatever is
appropriate for the current function.

Patch by Yiannis Tsiouris!

llvm-svn: 156459
 2012-05-09 01:50:09 +00:00
Akira Hatanaka
a53bdc878f Make register FP allocatable if the compiled function does not have dynamic 
allocas.

llvm-svn: 156458
 2012-05-09 01:38:13 +00:00
Akira Hatanaka
bd2f3d1c46 Expand 64-bit shifts if target ABI is O32. 
llvm-svn: 156457
 2012-05-09 00:55:21 +00:00
Richard Trieu
f0a7637b27 Remove unused variable to silence compiler warning. 
llvm-svn: 156456
 2012-05-09 00:30:21 +00:00
Jakob Stoklund Olesen
c7857568af Use a shared function for a common operation. 
llvm-svn: 156441
 2012-05-08 23:27:30 +00:00
Eric Christopher
255767a1d7 Remove excess semi-colons to quiet warnings. 
llvm-svn: 156416
 2012-05-08 20:45:04 +00:00
Sirish Pande
94592d3685 Update load/store instruction patterns in Hexagon V4. 
llvm-svn: 156411
 2012-05-08 19:50:20 +00:00
Akira Hatanaka
d276cdbd58 Define mips16 instruction formats. 
Patch by Reed Kotler.

llvm-svn: 156408
 2012-05-08 19:08:58 +00:00
Jakob Stoklund Olesen
989c6b112d s/CSR_Ghc/CSR_NoRegs/ 
Share the CalleeSavedRegs defs between all calling conventions having no
callee-saved registers.

Patch by Yiannis Tsiouris!

llvm-svn: 156382
 2012-05-08 15:07:29 +00:00
Craig Topper
77b1a4cee5 Remove 256-bit AVX non-temporal store intrinsics. Similar was previously done for 128-bit. 
llvm-svn: 156375
 2012-05-08 06:58:15 +00:00
Jakob Stoklund Olesen
cc0cf22b98 Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass(). 
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328
 2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen
63489eb1bd Fix bug in TRI::getCommonSuperRegClass(). 
Test cases for this code are coming. It is not used for anything yet.

llvm-svn: 156327
 2012-05-07 21:59:31 +00:00
Jakob Stoklund Olesen
d92280013d Add TRI::getCommonSuperRegClass(). 
This function is a generalization of getMatchingSuperRegClass() to the
symmetric case where both sides are using a sub-register index. It will
find a super-register class and sub-register indexes that make this
diagram commute:

                                   PreA
                       SuperRC  ---------->  RCA

                          |                   |
                          |                   |
                     PreB |                   | SubA
                          |                   |
                          |                   |
                          V                   V

                         RCB    ----------> SubRC
                                   SubB

This can be used to coalesce copies like:

  %vreg1:sub16 = COPY %vreg2:sub16; GR64:%vreg1, GR32: %vreg2

llvm-svn: 156317
 2012-05-07 19:14:58 +00:00
Chad Rosier
3e284d8bd6 Fix a regression from r147481. This combine should only happen if there is a 
single use.
rdar://11360370

llvm-svn: 156316
 2012-05-07 18:47:44 +00:00
Manman Ren
6fde9f74b4 X86: optimization for -(x != 0) 
This patch will optimize -(x != 0) on X86
FROM 
cmpl	$0x01,%edi
sbbl	%eax,%eax
notl	%eax
TO
negl %edi
sbbl %eax %eax

In order to generate negl, I added patterns in Target/X86/X86InstrCompiler.td:
def : Pat<(X86sub_flag 0, GR32:$src), (NEG32r GR32:$src)>;

rdar: 10961709
llvm-svn: 156312
 2012-05-07 18:06:23 +00:00
Eric Christopher
c2cd5bdf83 Add support for the 'x' constraint. 
Patch by Jack Carter.

llvm-svn: 156295
 2012-05-07 06:25:19 +00:00
Eric Christopher
87e8163c57 Add support for the 'l' constraint. 
Patch by Jack Carter.

llvm-svn: 156294
 2012-05-07 06:25:15 +00:00
Eric Christopher
af8eabbbd8 Add support for the 'c' constraint. 
Patch by Jack Carter.

llvm-svn: 156293
 2012-05-07 06:25:10 +00:00
Eric Christopher
0f1a0afa75 Add support for the 'P' constraint. 
Patch by Jack Carter.

llvm-svn: 156292
 2012-05-07 06:25:02 +00:00
Craig Topper
02644ca6b7 Fix some issues in the f16c instructions. 
llvm-svn: 156287
 2012-05-07 06:00:15 +00:00
Eric Christopher
a6552ba637 Add support for the 'O' constraint. 
Patch by Jack Carter.

llvm-svn: 156285
 2012-05-07 05:46:48 +00:00
Eric Christopher
5e1efebf09 Add support for the 'N' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156284
 2012-05-07 05:46:43 +00:00
Eric Christopher
e5a46b70b3 Add support for the 'L' inline asm constraint. 
Patch by Jack Carter.

llvm-svn: 156283
 2012-05-07 05:46:37 +00:00
Eric Christopher
267aa256cb Add support for the inline asm constraint 'K'. 
llvm-svn: 156282
 2012-05-07 05:46:29 +00:00
Craig Topper
c6d0bc2afc Add SSE4A MOVNTSS/MOVNTSD instructions. 
llvm-svn: 156281
 2012-05-07 05:36:19 +00:00
Eric Christopher
bf784be9ae Support the 'J' constraint. 
Patch by Jack Carter.

llvm-svn: 156280
 2012-05-07 03:13:42 +00:00
Eric Christopher
929ba63dcf Add support for the 'I' inline asm constraint. Also add tests 
from the previous 2 patches.

Patch by Jack Carter.

llvm-svn: 156279
 2012-05-07 03:13:32 +00:00
Eric Christopher
0c140afa87 Allow 64 bit integer values in gpu registers if arch and abi are 64 bit. 
Patch by Jack Carter.

llvm-svn: 156278
 2012-05-07 03:13:22 +00:00
Eric Christopher
6397520b96 When using inline asm constraints representing 
non-floating point general registers allow 8 and 16-bit
elements.

Patch by Jack Carter.

llvm-svn: 156277
 2012-05-07 03:13:16 +00:00
Craig Topper
4246b08208 Use MVT instead of EVT as the argument to all the shuffle decode functions. Simplify some of the decode functions. 
llvm-svn: 156268
 2012-05-06 19:46:21 +00:00
Craig Topper
b3b4c9476d Add VPERMQ/VPERMPD to the list of target specific shuffles that can be looked through for DAG combine purposes. 
llvm-svn: 156266
 2012-05-06 18:54:26 +00:00
Craig Topper
b95ee6cfc1 Add shuffle decode support for VPERMQ/VPERMPD. 
llvm-svn: 156265
 2012-05-06 18:44:02 +00:00
Jim Grosbach
f7461026c2 Nuke a few dead remnants of the CBE. 
llvm-svn: 156241
 2012-05-05 17:45:12 +00:00
Benjamin Kramer
7a9528b540 Add a new target hook "predictableSelectIsExpensive". 
This will be used to determine whether it's profitable to turn a select into a
branch when the branch is likely to be predicted.

Currently enabled for everything but Atom on X86 and Cortex-A9 devices on ARM.

I'm not entirely happy with the name of this flag, suggestions welcome ;)

llvm-svn: 156233
 2012-05-05 12:49:14 +00:00
Benjamin Kramer
39afd32d88 NVPTX: Initialize the UseF32FTZ flag. 
llvm-svn: 156232
 2012-05-05 11:22:02 +00:00
Eric Christopher
d0a426dbe4 Typo. 
llvm-svn: 156226
 2012-05-05 01:16:06 +00:00
David Blaikie
4f57670dab Fix warnings in release build. 
This fixes a couple of Clang warnings in release builds of LLVM:

* Missing return in ISelLowering
* Unused variable in NVPTXutil.cpp

llvm-svn: 156216
 2012-05-04 22:34:16 +00:00
Kevin Enderby
7bc52bcfad Tweak to the fix in r156212, as with the change in removing the shift the 
SignExtend32<22>(Val<<1) also needs to change to SignExtend32<21>(Val) .

llvm-svn: 156213
 2012-05-04 22:09:52 +00:00
Kevin Enderby
8c41cffe0b Fix a bug in the ARM disassembler for wide branch conditional instructions 
where the symbolic operand's displacement was incorrectly shifted left by 1.
rdar://11387046

llvm-svn: 156212
 2012-05-04 22:02:27 +00:00
Chandler Carruth
856e83e1c1 Fix a Clang warning in the new NVPTX backend: 
In file included from ../lib/Target/NVPTX/VectorElementize.cpp:53:
../lib/Target/NVPTX/NVPTX.h:44:3: warning: default label in switch which covers all enumeration values [-Wcovered-switch-default]
  default: assert(0 && "Unknown condition code");
  ^
1 warning generated.

The prevailing pattern in LLVM is to not use a default label, and instead to
use llvm_unreachable to denote that the switch in fact covers all return paths
from the function.

llvm-svn: 156209
 2012-05-04 21:35:49 +00:00
Justin Holewinski
4ca961430f This patch adds a new NVPTX back-end to LLVM which supports code generation for NVIDIA PTX 3.0. This back-end will (eventually) replace the current PTX back-end, while maintaining compatibility with it. 
The new target machines are:

nvptx (old ptx32) => 32-bit PTX
nvptx64 (old ptx64) => 64-bit PTX

The sources are based on the internal NVIDIA NVPTX back-end, and
contain more functionality than the current PTX back-end currently
provides.

NV_CONTRIB

llvm-svn: 156196
 2012-05-04 20:18:50 +00:00
Sebastian Pop
2b868d474e Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions. 
llvm-svn: 156195
 2012-05-04 19:53:56 +00:00
Preston Gurd
8de39bd4f6 Adds Intel Atom scheduling latencies to X86InstrSystem.td. 
llvm-svn: 156194
 2012-05-04 19:26:37 +00:00
Matt Beaumont-Gay
c6b2d69140 Pacify GCC's -Wreturn-type 
llvm-svn: 156189
 2012-05-04 18:34:27 +00:00
Hans Wennborg
b3c41d012d Make ARM and Mips use TargetMachine::getTLSModel() 
This moves the logic for selecting a TLS model to a single place,
instead of the previous three (ARM, Mips, and X86 which already
uses this function).

llvm-svn: 156162
 2012-05-04 09:40:39 +00:00
Craig Topper
88bf1f4404 Fix some loops to match coding standards. No functional change intended. 
llvm-svn: 156159
 2012-05-04 06:39:13 +00:00
Craig Topper
3845ea5b9e Fix up some spacing. No functional change. 
llvm-svn: 156158
 2012-05-04 06:18:33 +00:00
Craig Topper
71aab70d71 Simplify broadcast lowering code. No functional change intended. 
llvm-svn: 156157
 2012-05-04 05:49:51 +00:00
Craig Topper
6881f1067c Allow v16i16 and v32i8 shuffles to be rewritten as narrower shuffles. 
llvm-svn: 156156
 2012-05-04 04:44:49 +00:00