Commit Graph

165272 Commits

Author SHA1 Message Date
Saleem Abdulrasool
ee3f16f91b IR: fix documentation markup
Use `\brief` instead of `\Brief`.  NFC.

llvm-svn: 334627
2018-06-13 17:51:27 +00:00
Yaxun Liu
166d7e51aa [AMDGPU] Change enqueue kernel handle type
Currently the handle type is a global pointer which holds 8 bytes.
We need a larger type which hold 16 bytes, therefore change it
to [i64 x 2].

Differential Revision: https://reviews.llvm.org/D48094

llvm-svn: 334625
2018-06-13 17:31:51 +00:00
Simon Pilgrim
98546e502b [CostModel][X86] Test showing failure to recognise REVERSE shuffle mask if the elements come from the second src
llvm-svn: 334623
2018-06-13 17:12:11 +00:00
Dmitry Preobrazhensky
f3bc07c9d5 [AMDGPU][MC] Enabled parsing of relocations on VALU instructions
See bug 37566: https://bugs.llvm.org/show_bug.cgi?id=37566

Reviewers: artem.tamazov, arsenm, nhaehnle

Differential Revision: https://reviews.llvm.org/D47884

llvm-svn: 334622
2018-06-13 17:02:03 +00:00
Simon Pilgrim
21d47e6a7f [CostModel] Recognise BROADCAST shuffle mask if the elements come from the second src
llvm-svn: 334620
2018-06-13 16:52:02 +00:00
Andrea Di Biagio
b297f1e738 Revert: [llvm-mca] Flush the output stream before we start the analysis of a new code region. NFC
Not sure why, but it breaks buildbot clang-cmake-armv8-full.
It causes a failure in TEST 'Xray-armhf-linux :: TestCases/Posix/profiling-single-threaded.cc'.

llvm-svn: 334617
2018-06-13 16:33:52 +00:00
Simon Pilgrim
39a11cf87c [CostModel][X86] Test showing failure to recognise BROADCAST shuffle mask if the elements come from the second src
llvm-svn: 334616
2018-06-13 16:33:42 +00:00
Andrea Di Biagio
24185018fb [llvm-mca] Flush the output stream before we start the analysis of a new code region. NFC
llvm-svn: 334610
2018-06-13 15:43:56 +00:00
Dmitry Preobrazhensky
224cb6c72d [AMDGPU][MC][GFX8][GFX9] Allow LDS direct reads for BUFFER_LOAD_DWORDX2/X3/X4
See bug 37653: https://bugs.llvm.org/show_bug.cgi?id=37653

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D47885

llvm-svn: 334609
2018-06-13 15:32:46 +00:00
Sanjay Patel
59eabed7b6 [DAGCombiner] remove hasOneUse() check from fadd constants transform
We're constant folding here, so we shouldn't check uses. This matches
the IR optimizer behavior.

The x86 test shows the expected win. The AArch64 test shows something
else. This only seems to happen if the "generic" AArch64 CPU model is 
used by MachineCombiner, so I'll file a bug report to follow-up.

llvm-svn: 334608
2018-06-13 15:22:48 +00:00
Tom Stellard
968b81b26b AMDGPU: Move isSDNodeSourceOfDivergence() implementation to SITargetLowering
Summary:
The code that handles ISD:Register and ISD::CopyFromReg assumes
the target is amdgcn, so this is broken on r600.  We don't
need this analysis on r600 anyway so we can safely move
it to SITargetLowering.

Reviewers: alex-t, arsenm, nhaehnle

Reviewed By: arsenm

Subscribers: msearles, kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46298

llvm-svn: 334607
2018-06-13 15:06:37 +00:00
Sanjay Patel
aac81f364a [x86] add test for fadd with more than one use; NFC
The equivalent AArch64 test added at rL334556 isn't showing
the expected output from the DAGCombiner code change that 
would fix this example. That's a machine combiner bug from 
what I see.

llvm-svn: 334605
2018-06-13 15:01:07 +00:00
Cameron McInally
4fffc097ce [FPEnv] Expand constrained FP operations
Add a helper function to expand constrained FP operations as needed. 
Note that the Strict POWI operation is not handled in this patch since 
the format is slightly different from the others.

Differential Revision: https://reviews.llvm.org/D47491

llvm-svn: 334603
2018-06-13 14:32:12 +00:00
Hans Wennborg
de9c2ccba3 Do not enforce absolute path argv0 in windows
Even if we support no-canonical-prefix on
clang-cl(https://reviews.llvm.org/D47480), argv0 becomes absolute path
in clang-cl and that embeds absolute path in /showIncludes.

This patch removes such full path normalization from InitLLVM on
windows, and that removes absolute path from clang-cl output
(obj/stdout/stderr) when debug flag is disabled.

Patch by Takuto Ikuta!

Differential Revision https://reviews.llvm.org/D47578

llvm-svn: 334602
2018-06-13 14:29:26 +00:00
Guillaume Chatelet
ae44b4328d [llvm-exegesis] Fix buildbot - power was using native target for X86.
Reviewers: courbet

Reviewed By: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D48125

llvm-svn: 334601
2018-06-13 14:07:36 +00:00
Guillaume Chatelet
df2b898db8 [llvm-exegesis] Fix failing assert when creating Snippet for LAHF.
Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D48123

llvm-svn: 334599
2018-06-13 13:53:56 +00:00
Krzysztof Parzyszek
975a2623d5 Revert "Improve handling of COPY instructions with identical value numbers"
This reverts r334594, it breaks buildbots and fails with expensive checks.

llvm-svn: 334598
2018-06-13 13:49:06 +00:00
Guillaume Chatelet
8d818cafdb [llvm-exegesis] Cleaner design without mutable data.
Summary: Previous design was relying on the 'mutate' keyword and was quite confusing. This version separate mutable from immutable data and makes it clearer what changes and what doesn't.

Reviewers: courbet

Subscribers: tschuett, llvm-commits

Differential Revision: https://reviews.llvm.org/D48020

llvm-svn: 334596
2018-06-13 13:24:41 +00:00
Zoran Jovanovic
58b914129e [mips][microMIPS] Extending size reduction pass with LWP and SWP
Author: milena.vujosevic.janicic
Reviewers: sdardis
The patch extends size reduction pass for MicroMIPS.
It introduces reduction of two instructions into one instruction:
Two SW instructions are transformed into one SWP instrucition.
Two LW instructions are transformed into one LWP instrucition.
Differential Revision: https://reviews.llvm.org/D39115

llvm-svn: 334595
2018-06-13 12:51:37 +00:00
Krzysztof Parzyszek
178be651dc Improve handling of COPY instructions with identical value numbers
Differential Revision: https://reviews.llvm.org/D48102

llvm-svn: 334594
2018-06-13 12:47:17 +00:00
Sanjay Patel
434596cb1e [x86] eliminate even more sign-bit tests with vector select
This shortcoming was noted in D47330, and the test diffs show we already 
had other examples where we failed to fold to a SHRUNKBLEND:

/// Dynamic (non-constant condition) vector blend where only the sign bits
/// of the condition elements are used. This is used to enforce that the
/// condition mask is not valid for generic VSELECT optimizations.

This patch implements an idea from D48043 and would obsolete that patch 
because it catches more cases (notable the AVX1 case that was missed there). 
All we're doing is allowing the existing transform to fire more often by 
removing the post-legalize constraint. All of the relevant feature checks 
and other predicates are left as-is.

Differential Revision: https://reviews.llvm.org/D48078

llvm-svn: 334592
2018-06-13 12:28:32 +00:00
Alex Bradbury
446ce455bc [RISCV] Add codegen support for atomic load/stores with RV32A
Fences are inserted according to table A.6 in the current draft of version 2.3
of the RISC-V Instruction Set Manual, which incorporates the memory model
changes and definitions contributed by the RISC-V Memory Consistency Model
task group.

Instruction selection failures will now occur for 8/16/32-bit atomicrmw and 
cmpxchg operations when targeting RV32IA until lowering for these operations 
is added in a follow-on patch.

Differential Revision: https://reviews.llvm.org/D47589

llvm-svn: 334591
2018-06-13 12:04:51 +00:00
Alex Bradbury
e0603b95db [RISCV] Codegen support for atomic operations on RV32I
This patch adds lowering for atomic fences and relies on AtomicExpandPass to
lower atomic loads/stores, atomic rmw, and cmpxchg to __atomic_* libcalls.

test/CodeGen/RISCV/atomic-* are modelled on the exhaustive
test/CodeGen/PPC/atomics-regression.ll, and will prove more useful once RV32A
codegen support is introduced.

Fence mappings are taken from table A.6 in the current draft of version 2.3 of
the RISC-V Instruction Set Manual, which incorporates the memory model changes
and definitions contributed by the RISC-V Memory Consistency Model task group.

Differential Revision: https://reviews.llvm.org/D47587

llvm-svn: 334590
2018-06-13 11:58:46 +00:00
Simon Pilgrim
b9228e95f8 [SLPVectorizer] getSameOpcode - remove useless cast [NFC]
There's no need to cast the base Value to an Instruction

llvm-svn: 334588
2018-06-13 10:49:24 +00:00
Simon Pilgrim
bf4a2effd1 [SLPVectorizer] getSameOpcode - remove unusued alternate code [NFC]
We early-out for the case where we don't use alternate opcodes, so no need to check for it later.

llvm-svn: 334587
2018-06-13 10:14:27 +00:00
Clement Courbet
e3e2fa9c0a [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.
Summary:
For targets I'm not familiar with, I've automatically made the "default to 1 for each resource" behaviour explicit in the td files.
For more obvious cases, I've ventured a fix.

Some notes:
 - Exynos is especially fishy.
 - AArch64SchedThunderX2T99.td had some truncated entries. If I understand correctly, the person who wrote that interpreted the ResourceCycle as a range. I made the decision to use the upper/lower bound for consistency with the 'Latency' value. I'm sure there is a better choice.
 - The change to X86ScheduleBtVer2.td is an NFC, it just makes values more explicit.

Also see PR37310.

Reviewers: RKSimon, craig.topper, javed.absar

Subscribers: kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D46356

llvm-svn: 334586
2018-06-13 09:41:49 +00:00
Hans Wennborg
aa23250926 GettingStarted.rst: Fix 'If you you' typo (PR37787)
llvm-svn: 334584
2018-06-13 09:11:10 +00:00
Hiroshi Inoue
c50f941cad [PowerPC] fix trivial typos in comment, NFC
llvm-svn: 334583
2018-06-13 08:54:13 +00:00
Hans Wennborg
a4fac8416a Fix -DLLVM_ENABLE_THREADS=OFF build after r334537
llvm-svn: 334582
2018-06-13 08:43:03 +00:00
Pavel Labath
dd69f934b2 Fix "Optional" is ambiguous error on some bots
llvm-svn: 334580
2018-06-13 08:29:19 +00:00
Hiroshi Inoue
2dde032c9a [PowerPC] avoid verification failure due to PowerPC VSX Swap Removal pass
This patch fixes a failure in lnt tests with -verify-machineinstrs option.
When VSX Swap Removal pass swaps two register operands, it did not maintain kill flags associated with operands. This patch swaps flags as well as register number to avoid inconsistent kill flags information.

llvm-svn: 334579
2018-06-13 08:25:14 +00:00
Pavel Labath
740338b7fa [DWARF/AccelTable] Remove getDIESectionOffset for DWARF v5 entries
Summary:
This method was not correct for entries in DWO files as it assumed it
could just add up the CU and DIE offsets to get the absolute DIE offset.
This is not correct for the DWO files, as here the CU offset will
reference the skeleton unit, whereas the DIE offset will be the offset
in the full unit in the DWO file.

Unfortunately, this means that we are not able to determine the absolute
DIE offset using the information in the .debug_names section alone,
which means we have to offload some of this work to the users of this
class.

To demonstrate how this can be done, I've added/fixed the ability to
lookup entries using accelerator tables in DWO files in llvm-dwarfdump.
To make this happen, I've needed to make two extra changes in other
classes:
- made the DWARFContext method to lookup a CU based on the section
  offset public. I've needed this functionality to lookup a CU, and this
  seems like a useful thing in general.
- made DWARFUnit::getDWOId call extractDIEsIfNeeded. Before this, the
  DWOId was filled in only if the root DIE happened to be parsed
  before we called the accessor. Since the lazy parsing is supposed to
  happen under the hood, calling extractDIEsIfNeeded seems appropriate.

Reviewers: JDevlieghere, aprantl, dblaikie

Subscribers: mgrang, llvm-commits

Differential Revision: https://reviews.llvm.org/D48009

llvm-svn: 334578
2018-06-13 08:14:27 +00:00
Craig Topper
45edfd5c6f [X86] Remove masking from avx512vbmi2 concat and shift by immediate intrinsics. Use select in IR instead.
llvm-svn: 334576
2018-06-13 07:19:21 +00:00
Bill Wendling
164f4125a2 Set the code model when specified.
llvm-svn: 334571
2018-06-13 05:53:59 +00:00
Tom Stellard
fa1ab0b0a2 utils/release: Add merge-git.sh
Summary:
This script allows you to use git to backport a commit to a stable
branch while generating the exact same commit message (ignoring
whitespace) that you would get from using the merge.sh script with svn.

Reviewers: hansw

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D47760

llvm-svn: 334568
2018-06-13 05:14:10 +00:00
Max Kazantsev
55e622cae0 [SimplifyIndVars] Ignore dead users
IndVarSimplify sometimes makes transforms basing on users that are trivially dead. In particular,
if DCE wasn't run before it, there may be a dead `sext/zext` in loop that will trigger widening
transforms, however it makes no sense to do it.

This patch teaches IndVarsSimplify ignore the mist trivial cases of that.

Differential Revision: https://reviews.llvm.org/D47974
Reviewed By: sanjoy

llvm-svn: 334567
2018-06-13 02:25:32 +00:00
Ahmed Bougacha
80c0e9306e Revert "Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build"
This reverts commit r334543.

My understanding is, that commit is intended to make the llvm-build
invocation have a correct "--enable-optional-components" value, but:
- it already has a value: it's quoted in the command line a few lines
  below, and, if I hack llvm-build to print sys.argv, it does look correct:
    -- llvm-build output: ['.../utils/llvm-build/llvm-build',
      '--native-target', 'X86', '--enable-targets', 'X86;ARM;AArch64',
      '--enable-optional-components', '',
      '--write-library-table',
      '.../build/tools/llvm-config/LibraryDependencies.inc',
      '--write-cmake-fragment', '.../build/LLVMBuild.cmake']
- the " " string seems to evaluate to TRUE in CMake (*sigh*), so this
  basically force-enables LLVM_USE_INTEL_JITEVENTS, regardless of the
  value of the option.
  On Darwin, JITEvents is not supported, so this bypasses that OS check
  but is guaranteed to fail later.

llvm-svn: 334566
2018-06-13 02:16:01 +00:00
Craig Topper
73c6ebc8bf [X86] Mark all instructions that have masked store semantics with NotMemoryFoldable. Remove dependency on SchedRW from memory table autogenerator.
Previously we were whitelisting in instructions based on their SchedRW value. With the masked store instructions explicitly removed via NotMemoryFoldable, we don't seem to need this check anymore.

llvm-svn: 334563
2018-06-13 00:04:08 +00:00
Craig Topper
7b76729ea5 [X86] Remove VPCOMPRESSB/W from the autogenerated load folding table.
llvm-svn: 334562
2018-06-13 00:04:04 +00:00
Stanislav Mekhanoshin
017429bc2b [AMDGPU] DAG combine to produce V_PERM_B32
Differential Revision: https://reviews.llvm.org/D48099

llvm-svn: 334559
2018-06-12 23:50:37 +00:00
Sanjay Patel
6ab778401f [AArch64] add tests for fadd with more than one use; NFC
llvm-svn: 334556
2018-06-12 22:50:37 +00:00
Raphael Isemann
47ed815a1e Added missing include to AMDHSAKernelDescriptor.h
We use size_t in this header, so we also need to include
cstddef to make it compile. Fixes the module builds.

llvm-svn: 334555
2018-06-12 22:40:20 +00:00
Krzysztof Parzyszek
90f9f3ddd4 [DAGCombiner] Recognize more patterns for ABS
Differential Revision: https://reviews.llvm.org/D47831

llvm-svn: 334553
2018-06-12 21:51:49 +00:00
Craig Topper
78d32522b9 [X86] add avx512 tests for potentially miscompiling cvttp2si/cvttp2ui (PR37751).
llvm-svn: 334551
2018-06-12 21:42:42 +00:00
Reid Kleckner
d507aa875b Remove malloc.h include from Intel JIT events code
llvm-svn: 334547
2018-06-12 21:15:27 +00:00
Reid Kleckner
903c5152f8 Add null check to Intel JIT event listener
llvm-svn: 334544
2018-06-12 20:54:11 +00:00
Reid Kleckner
e817bea6ed Fix how LLVMOPTIONALCOMPONENTS is passed to llvm-build
Patch by Force.Charlie-I

If LLVM_USE_INTEL_JITEVENTS and LLVM_USE_OPROFILE  not set,
"${LLVMOPTIONALCOMPONENTS}" is empty, but
**--enable-optional-components** need arg, Cause
**--write-library-table** to be skipped parsed.

Differential Revision: https://reviews.llvm.org/D47982

llvm-svn: 334543
2018-06-12 20:53:46 +00:00
Lang Hames
814b934314 [ORC] Add a fallback definition generator for VSOs.
If a VSO has a fallback definition generator attached it will be called during
lookup (and lookupFlags) for any unresolved symbols. The definition generator
can add new definitions to the VSO for any unresolved symbol. This allows VSOs
to generate new definitions on demand.

The immediate use case for this code is supporting VSOs that can import
definitions found via dlsym on demand.

llvm-svn: 334538
2018-06-12 20:43:18 +00:00
Lang Hames
86330a7ffe [ORC] Refactor blocking lookup logic into the blockingLookup function, and
implement existing blocking lookups (the lookup function) and
JITSymbolResolverAdapter on top of that.

llvm-svn: 334537
2018-06-12 20:43:17 +00:00
Lang Hames
0272690143 [RuntimeDyld] Add an assert to catch misbehaving symbol resolvers.
Resolvers are required to find results for all requested symbols or return an
error, but if a resolver fails to adhere to this contract (by returning results
for only a subset of the requested symbols) then this code will infinite loop.
This assertion catches resolvers that fail to adhere to the contract.

llvm-svn: 334536
2018-06-12 20:43:17 +00:00