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3209 Commits

Author SHA1 Message Date
Douglas Gregor
d11c0d2ab8 Update the Clang attribute emitter to handle attributes of 'version' 
kind, and fix serialization/deserialization of IdentifierInfo
attributes. These are requires for the new 'availability' attribute.

llvm-svn: 128130
 2011-03-23 01:05:46 +00:00
Bill Wendling
52c4596a0f Call static functions so that they aren't left unused. 
llvm-svn: 128020
 2011-03-21 21:08:27 +00:00
Bill Wendling
9adf1c9edd A WIP commit of the InstAlias printing cleanup. This code will soon replace the 
code below it. Even though it looks very similar, it will match more precisely
and geneate better functions in the long run.

llvm-svn: 127991
 2011-03-21 08:59:17 +00:00
Bill Wendling
4cdb29548b Add the IAPrinter class. 
This is a helper class that will make it easier to say which InstAliases can be
printed and which cannot (because of ambiguity).

llvm-svn: 127990
 2011-03-21 08:40:31 +00:00
Bill Wendling
e3b0820ad4 * Add classes that support the "feature" information. 
* Move the code that emits the reg in reg class matching into its own function.

llvm-svn: 127988
 2011-03-21 08:31:53 +00:00
Owen Anderson
c23c6e0c1a Thumb2 PC-relative loads require a fixup rather than just an immediate. 
llvm-svn: 127888
 2011-03-18 17:42:55 +00:00
NAKAMURA Takumi
cdd69c874f raw_ostream: [PR6745] Tweak formatting (double)%e for Windows hosts. 
On MSVCRT and compatible, output of %e is incompatible to Posix by default. Number of exponent digits should be at least 2. "%+03d"

FIXME: Implement our formatter in future!
llvm-svn: 127872
 2011-03-18 09:30:10 +00:00
NAKAMURA Takumi
82c316b78a lit/ProgressBar.py: [PR7919] Improve line wrap for XN-incapable terminals. 
On Win32 console, emitting char to col#79 causes linefeed, and the cursor will not return to col#79 upper line with backspace.

llvm-svn: 127696
 2011-03-15 21:07:44 +00:00
Evan Cheng
14eff5d627 - Add "Bitcast" target instruction property for instructions which perform 
nothing more than a bitcast.
- Teach tablegen to automatically infer "Bitcast" property.

llvm-svn: 127667
 2011-03-15 05:09:26 +00:00
Sean Callanan
5a51ccdc0f X86 table-generator and disassembler support for the AVX 
instruction set.  This code adds support for the VEX prefix
and for the YMM registers accessible on AVX-enabled
architectures.  Instruction table support that enables AVX
instructions for the disassembler is in an upcoming patch.

llvm-svn: 127644
 2011-03-15 01:23:15 +00:00
Owen Anderson
49965661d5 Ignore isCodeGenOnly instructions when generating diassembly tables. 
llvm-svn: 127619
 2011-03-14 20:58:49 +00:00
Jim Grosbach
973ab94013 Trailing whitespace. 
llvm-svn: 127592
 2011-03-14 17:32:49 +00:00
Francois Pichet
0e434150f9 Correct small comment order typo. 
llvm-svn: 127575
 2011-03-14 02:30:32 +00:00
Jim Grosbach
a87f223848 Remove no-longer-correct special case for disasm of ARM BL instructions. 
llvm-svn: 127517
 2011-03-12 01:05:29 +00:00
Jim Grosbach
daffeb06fb Pseudo-ize the ARM 'B' instruction. 
llvm-svn: 127510
 2011-03-11 23:24:15 +00:00
Jim Grosbach
2226dfbea2 Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127509
 2011-03-11 23:15:02 +00:00
Jim Grosbach
01a937ac07 Remove dead code. These ARM instruction definitions no longer exist. 
llvm-svn: 127508
 2011-03-11 23:11:41 +00:00
Jim Grosbach
009af69d6d Pseudo-ize VMOVDcc and VMOVScc. 
llvm-svn: 127506
 2011-03-11 23:09:50 +00:00
Jim Grosbach
b480da2317 Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127491
 2011-03-11 20:51:07 +00:00
Jim Grosbach
ee6075cda5 ARM VDUPfd and VDUPfq can just be patterns. The instruction is the same 
as for VDUP32d and VDUP32q, respectively.

llvm-svn: 127489
 2011-03-11 20:44:08 +00:00
Jim Grosbach
cb57d3b1d9 Remove dead code. These ARM instruction definitions don't exist. 
llvm-svn: 127488
 2011-03-11 20:38:18 +00:00
Jim Grosbach
3329263352 ARM VDUPLNfq and VDUPLNfd definitions can just be Pat<>s for VDUPLN32q 
and VDUPLN32d, respectively.

llvm-svn: 127486
 2011-03-11 20:31:17 +00:00
Jim Grosbach
431682981d ARM VREV64df and VREV64qf can just be patterns. The instruction is the same 
as for VREV64d32 and VREV64q32, respectively.

llvm-svn: 127485
 2011-03-11 20:18:05 +00:00
Jim Grosbach
9e8cf109dc Add missing 'return on failure'. Previously we'd crash after emitting 
the diagnostic.

llvm-svn: 127480
 2011-03-11 19:52:52 +00:00
Jim Grosbach
c7548fce48 Teach TableGen to pre-calculate register enum values when creating the 
CodeGenRegister entries. Use this information to more intelligently build
the literal register entires in the DAGISel matcher table. Specifically,
use a single-byte OPC_EmitRegister entry for registers with a value of
less than 256 and OPC_EmitRegister2 entry for registers with a larger value.

rdar://9066491

llvm-svn: 127456
 2011-03-11 02:19:02 +00:00
Jim Grosbach
6e41ec016b Make the register enum value part of the CodeGenRegister struct. 
llvm-svn: 127448
 2011-03-11 01:33:54 +00:00
Jim Grosbach
2c9ce71360 Trailing whitespace. 
llvm-svn: 127447
 2011-03-11 01:27:24 +00:00
Jim Grosbach
9834ed0ef4 Trailing whitespace. 
llvm-svn: 127446
 2011-03-11 01:19:05 +00:00
Jim Grosbach
9cddc3746d Tidy up since ARM MOVCCi and MOVCCi16 are now pseudos. 
llvm-svn: 127445
 2011-03-11 01:16:49 +00:00
Jim Grosbach
1986d9ac8f Properly pseudo-ize MOVCCr and MOVCCs. 
llvm-svn: 127434
 2011-03-10 23:56:09 +00:00
Jim Grosbach
41694b91ad Memory barrier instructions don't need special handling in tblgen anymore. 
llvm-svn: 127419
 2011-03-10 19:05:48 +00:00
Stuart Hastings
f4420e43f1 Stop building PPC parts on OSX. Radar 8637926. 
llvm-svn: 127262
 2011-03-08 19:28:28 +00:00
NAKAMURA Takumi
c989c9adfa Use $(ECHOPATH) to make llvm-lit from llvm-lit.in. 
llvm-svn: 127240
 2011-03-08 12:25:19 +00:00
Bill Wendling
db6712f416 Don't show commands. 
llvm-svn: 127224
 2011-03-08 08:34:49 +00:00
Bill Wendling
958e854f40 Rename the narrow shift right immediate operands to "shr_imm*" operands. Also 
expand the testing of the narrowing shift right instructions.

No functionality change.

llvm-svn: 127193
 2011-03-07 23:38:41 +00:00
Bill Wendling
e07a701cb9 Don't keep the log files around. Just pipe to a log file instead. 
llvm-svn: 127155
 2011-03-07 07:37:37 +00:00
Jakob Stoklund Olesen
d415589edc Revert r127073: "Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for alternative of $(ECHO)." 
It broke the llvm-gcc-native-mingw32 buildbot, and we need all of them to be green for the 2.9 branch.

Takumi, please reapply after we branch, preferably with a fix ;-)

llvm-svn: 127107
 2011-03-05 18:55:06 +00:00
NAKAMURA Takumi
0afd9bcaec utils/lit/lit/TestRunner.py: bash is available with MSYS on Python/W32. Then we can execute "bash tests". 
llvm-svn: 127074
 2011-03-05 09:46:53 +00:00
NAKAMURA Takumi
9cab0faea2 Introduce $(ECHOPATH) to print DOSish path string on MSYS bash for alternative of $(ECHO). 
On mingw and python/w32, lit would not be expected to understand MSYS-style path.

llvm-svn: 127073
 2011-03-05 09:46:45 +00:00
NAKAMURA Takumi
355800852d On Windows hosts, Python scripts in test/Scripts did not accept binary files from stdin. The environment variable "PYTHONUNBUFFERED" makes stdin as binary. Thanks to Danil Malyshev! 
llvm-svn: 127072
 2011-03-05 09:46:36 +00:00
David Greene
125709b0ea Fix the case where the number of jobs is less than the 
number of threads.  In that case make the number of threads
equal to the number of jobs and launch one jobs on each
thread.  This makes things work like make -j.

llvm-svn: 127045
 2011-03-04 23:02:52 +00:00
Bob Wilson
e24bee9ce8 TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
llvm-svn: 126931
 2011-03-03 07:19:52 +00:00
Bob Wilson
42f80596ca pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
 2011-03-03 01:41:01 +00:00
John McCall
8346b49836 Teach the clang attribute emitter about InheritableParamAttr. 
Intended to be atomic with clang r126828.

llvm-svn: 126827
 2011-03-02 04:00:52 +00:00
Oscar Fuentes
15a668f50b Fixes warnings emitted by Visual Studio 2010 compiler. 
Patch by Erik Olofsson!

llvm-svn: 126796
 2011-03-01 23:11:57 +00:00
Jim Grosbach
3b72823981 trailing whitespace. 
llvm-svn: 126733
 2011-03-01 01:39:05 +00:00
Jim Grosbach
fbdcd70f4b Generalize the register matching code in DAGISel a bit. 
llvm-svn: 126731
 2011-03-01 01:37:19 +00:00
Bill Wendling
304dda7810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
NAKAMURA Takumi
9c6821e474 Don't install libUnitTestMain.a. It might be useless without gtest headers. 
llvm-svn: 126632
 2011-02-28 05:18:07 +00:00
Bill Wendling
91cce6cc1d A new TableGen feature! (Not turned on just yet.) 
InstAlias<{alias}, {aliasee}>;

The InstAlias instruction should be able to go from the MCInst to the
{alias}. All of the information is there to match the MCInst with the
{aliasee}. From there, it's a simple matter to emit the {alias}, with the
correct operands from the {aliasee}.

The code this patch generates can be used by the InstPrinter to automatically
print out the alias without having to write special C++ code to handle the
situation.

This is a WIP, and therefore are several limitations. For instance, it cannot
handle AsmOperands at the moment. It also doesn't know what to do when two
{alias}es match the same {aliasee}. (Currently, it just ignores those two cases
and allows the printInstruction method to handle them.)

llvm-svn: 126538
 2011-02-26 03:09:12 +00:00