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Author SHA1 Message Date
Bruno Cardoso Lopes
fcd7917ed0 Also add the late notes for Mips in the current release note 
llvm-svn: 129122
 2011-04-08 03:06:22 +00:00
Johnny Chen
16ed2c18a0 Add sanity checking for bad register specifier(s) for the DPFrm instructions. 
Add more test cases to exercise the logical branches related to the above change.

llvm-svn: 129117
 2011-04-08 00:29:09 +00:00
Rafael Espindola
c2955605da Update tests 
llvm-svn: 129116
 2011-04-07 23:51:25 +00:00
Rafael Espindola
19119075c4 Micro optimization and improved similarity with gas' output: 
When two section names share a suffix, reuse the entry in shstrtab.

llvm-svn: 129115
 2011-04-07 23:21:52 +00:00
Devang Patel
47e1db49c9 Do not let debug info interfer with branch folding. 
llvm-svn: 129114
 2011-04-07 23:11:25 +00:00
Johnny Chen
0b8e3b20f7 Add a VEXT test. 
llvm-svn: 129111
 2011-04-07 22:04:01 +00:00
Bill Wendling
342ba5c4b6 Replace the old algorithm that emitted the "print the alias for an instruction" 
with the newer, cleaner model. It uses the IAPrinter class to hold the
information that is needed to match an instruction with its alias. This also
takes into account the available features of the platform.

There is one bit of ugliness. The way the logic determines if a pattern is
unique is O(N**2), which is gross. But in reality, the number of items it's
checking against isn't large. So while it's N**2, it shouldn't be a massive time
sink.

llvm-svn: 129110
 2011-04-07 21:20:06 +00:00
Rafael Espindola
61e0c74936 If present, use gold's support for getting a file view. This prevents having 
to map the file both in the linker and in the plugin.

llvm-svn: 129109
 2011-04-07 21:11:00 +00:00
Evan Cheng
9049eb2113 Add option to emit @llvm.trap as a function call instead of a trap instruction. rdar://9249183. 
llvm-svn: 129107
 2011-04-07 20:31:12 +00:00
Rafael Espindola
a27969f537 Add support for .skip. 
Patch by Roman Divacky.
Fixes PR9361.

llvm-svn: 129106
 2011-04-07 20:26:23 +00:00
Akira Hatanaka
dcc8678bd5 Fix indentation. 
llvm-svn: 129105
 2011-04-07 20:25:10 +00:00
Akira Hatanaka
b8304b2c15 Update ATUsed every time after expandRegLargeImmPair is called. 
llvm-svn: 129104
 2011-04-07 20:23:26 +00:00
Mon P Wang
9aa67ff50a Fixed encoding for VEXTqf 
llvm-svn: 129101
 2011-04-07 19:56:12 +00:00
Andrew Trick
36a1759769 Added a check in the preRA scheduler for potential interference on a 
induction variable. The preRA scheduler is unaware of induction vars,
so we look for potential "virtual register cycles" instead.

Fixes <rdar://problem/8946719> Bad scheduling prevents coalescing

llvm-svn: 129100
 2011-04-07 19:54:57 +00:00
Akira Hatanaka
24e15bbe94 Fix handling of functions with internal linkage. 
llvm-svn: 129099
 2011-04-07 19:51:44 +00:00
Johnny Chen
5d23dd2116 Add sanity checking for invalid register encodings for signed/unsigned extend instructions. 
Add some test cases.

llvm-svn: 129098
 2011-04-07 19:28:58 +00:00
Johnny Chen
7198a60b9a Add sanity checking for invalid register encodings for saturating instructions. 
llvm-svn: 129096
 2011-04-07 19:02:08 +00:00
Jakob Stoklund Olesen
3e349f2950 Recompute hasPHIKill flags when shrinking live intervals. 
PHI values may be deleted, causing the flags to be wrong. This fixes PR9616.

llvm-svn: 129092
 2011-04-07 18:43:14 +00:00
Johnny Chen
ecc113f223 Add some more comments about checkings of invalid register numbers. 
And two test cases.

llvm-svn: 129090
 2011-04-07 18:33:19 +00:00
Rafael Espindola
a13eab4837 Expose more passes to the C API. 
llvm-svn: 129087
 2011-04-07 18:20:46 +00:00
Jakob Stoklund Olesen
aace1636b6 Avoid moving iterators when the previous block was just visited. 
llvm-svn: 129081
 2011-04-07 17:27:50 +00:00
Jakob Stoklund Olesen
1791098020 Prefer multiplications to divisions. 
llvm-svn: 129080
 2011-04-07 17:27:48 +00:00
Jakob Stoklund Olesen
402a4daae6 Extract SpillPlacement::addLinks for handling the special transparent blocks. 
llvm-svn: 129079
 2011-04-07 17:27:46 +00:00
Devang Patel
17670a995c While hoisting common code from if/else, hoist debug info intrinsics if they match. 
llvm-svn: 129078
 2011-04-07 17:27:36 +00:00
Tanya Lattner
3deb96fad7 Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector type (vectors of size 3). Also included test cases. 
llvm-svn: 129074
 2011-04-07 15:24:20 +00:00
Jay Foad
9351e0c03e Fix a bit of nonsense. 
llvm-svn: 129073
 2011-04-07 12:41:09 +00:00
Chris Lattner
c0cc11ce0f add faust too 
llvm-svn: 129053
 2011-04-07 03:09:21 +00:00
Chris Lattner
af5e910e60 add a few late stragglers. 
llvm-svn: 129052
 2011-04-07 03:08:22 +00:00
Sean Callanan
b1e6d05325 Fixed a bug where missing EDInstInfo would cause 
tokenization to crash and burn.

llvm-svn: 129051
 2011-04-07 01:56:01 +00:00
Johnny Chen
4c81015af7 Sanity check MSRi for invalid mask values and reject it as invalid. 
rdar://problem/9246844

llvm-svn: 129050
 2011-04-07 01:37:34 +00:00
Eli Friedman
b0e846a68c PR9634: Don't unconditionally tell the AliasSetTracker that the PreheaderLoad 
is equivalent to any other relevant value; it isn't true in general.
If it is equivalent, the LoopPromoter will tell the AST the equivalence.
Also, delete the PreheaderLoad if it is unused.

Chris, since you were the last one to make major changes here, can you check
that this is sane?

llvm-svn: 129049
 2011-04-07 01:35:06 +00:00
Johnny Chen
1f028bb23e The ARM disassembler was not recognizing USADA8 instruction. Need to add checking for register values 
for USAD8 and USADA8.

rdar://problem/9247060

llvm-svn: 129047
 2011-04-07 01:05:52 +00:00
Evan Cheng
859dff2c87 Change -arm-divmod-libcall to a target neutral option. 
llvm-svn: 129045
 2011-04-07 00:58:44 +00:00
Evan Cheng
1d3691e071 Remove dead code. rdar://9221736. 
llvm-svn: 129044
 2011-04-07 00:56:37 +00:00
Johnny Chen
523f8f38f7 Should also check SMLAD for invalid register values. 
rdar://problem/9246650

llvm-svn: 129042
 2011-04-07 00:50:25 +00:00
Devang Patel
bb234bb5dd Simplify. isIdenticalToWhenDefined() checks opcode. 
llvm-svn: 129041
 2011-04-07 00:30:15 +00:00
Nick Lewycky
04fdd20e58 Set unnamed_addr on strings created through the IRBuilder. 
llvm-svn: 129040
 2011-04-07 00:14:29 +00:00
Nick Lewycky
fccee4ca24 Add support for ArrayRef in IRBuilder's CreateCall. 
llvm-svn: 129039
 2011-04-07 00:03:25 +00:00
Owen Anderson
37b60bdf09 Teach the ARM peephole optimizer that RSB, RSC, ADC, and SBC can be used for folded comparisons, just like ADD and SUB. 
llvm-svn: 129038
 2011-04-06 23:35:59 +00:00
Owen Anderson
7f766b61a1 Cleanups from Jim: remove redundant constraints and a dead FIXME. 
llvm-svn: 129036
 2011-04-06 22:45:55 +00:00
Devang Patel
12a95842b2 While folding branch to a common destination into a predecessor, copy dbg values also. 
llvm-svn: 129035
 2011-04-06 22:37:20 +00:00
Jim Grosbach
0510dc2765 Tidy up. 
llvm-svn: 129034
 2011-04-06 22:35:47 +00:00
Johnny Chen
81aa7d84be A8.6.393 
The ARM disassembler should reject invalid (type, align) encodings as invalid instructions.

So, instead of:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

	vst2.32	{d0, d2}, [r3, :256], r3

we now have:
Opcode=1641 Name=VST2b32_UPD Format=ARM_FORMAT_NLdSt(30)
 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10  9  8  7  6  5  4  3  2  1  0 
-------------------------------------------------------------------------------------------------
| 1: 1: 1: 1| 0: 1: 0: 0| 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 0: 0| 1: 0: 0: 1| 1: 0: 1: 1| 0: 0: 1: 1|
-------------------------------------------------------------------------------------------------

mc-input.txt:1:1: warning: invalid instruction encoding
0xb3 0x9 0x3 0xf4
^

llvm-svn: 129033
 2011-04-06 22:14:48 +00:00
Jim Grosbach
3b01595efd tidy up. 
llvm-svn: 129032
 2011-04-06 22:13:52 +00:00
Jakob Stoklund Olesen
b59d7e2dea Also account for the spill code that would be inserted in live-through blocks with interference. 
llvm-svn: 129030
 2011-04-06 21:32:41 +00:00
Jakob Stoklund Olesen
7bd327adbc Abort the constraint calculation early when all positive bias is lost. 
Without any positive bias, there is nothing for the spill placer to to. It will
spill everywhere.

llvm-svn: 129029
 2011-04-06 21:32:38 +00:00
Nick Lewycky
a980fa69e8 Fix typo in doxy-comment. 
llvm-svn: 129028
 2011-04-06 20:54:07 +00:00
Johnny Chen
96fd9620c8 A8.6.92 MCR (Encoding A1): if coproc == '101x' then SEE "Advanced SIMD and VFP" 
Since these "Advanced SIMD and VFP" instructions have more specfic encoding bits
specified, if coproc == 10 or 11, we should reject the insn as invalid.

rdar://problem/9239922
rdar://problem/9239596

llvm-svn: 129027
 2011-04-06 20:49:02 +00:00
Nick Lewycky
505e20340f Fix comment to use llvm 2.x syntax. 
llvm-svn: 129025
 2011-04-06 20:38:44 +00:00
Nick Lewycky
f2d78099ce Replace const std::vector& with ArrayRef in the type creation APIs. 
llvm-svn: 129024
 2011-04-06 20:28:34 +00:00