llvm-mirror/test/MC/Mips/mips64shift.ll
Daniel Sanders 70d63fbd2e [mips] Remove CPU-only triples from llvm-objdump commands.
Summary: They aren't necessary since llvm-objdump can auto-detect the architecture.

Reviewers: sdardis

Subscribers: jfb, dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D20904

llvm-svn: 271653
2016-06-03 10:22:22 +00:00

49 lines
1.1 KiB
LLVM

; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 -disable-mips-delay-filler %s -o - \
; RUN: | llvm-objdump -disassemble - | FileCheck %s
; RUN: llc -march=mips64el -filetype=obj -mcpu=mips64r2 %s -o - \
; RUN: | llvm-objdump -disassemble - | FileCheck %s
define i64 @f3(i64 %a0) nounwind readnone {
entry:
; CHECK: dsll ${{[0-9]+}}, ${{[0-9]+}}, 10
%shl = shl i64 %a0, 10
ret i64 %shl
}
define i64 @f4(i64 %a0) nounwind readnone {
entry:
; CHECK: dsra ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = ashr i64 %a0, 10
ret i64 %shr
}
define i64 @f5(i64 %a0) nounwind readnone {
entry:
; CHECK: dsrl ${{[0-9]+}}, ${{[0-9]+}}, 10
%shr = lshr i64 %a0, 10
ret i64 %shr
}
define i64 @f6(i64 %a0) nounwind readnone {
entry:
; CHECK: dsll32 ${{[0-9]+}}, ${{[0-9]+}}, 8
%shl = shl i64 %a0, 40
ret i64 %shl
}
define i64 @f7(i64 %a0) nounwind readnone {
entry:
; CHECK: dsra32 ${{[0-9]+}}, ${{[0-9]+}}, 8
%shr = ashr i64 %a0, 40
ret i64 %shr
}
define i64 @f8(i64 %a0) nounwind readnone {
entry:
; CHECK: dsrl32 ${{[0-9]+}}, ${{[0-9]+}}, 8
%shr = lshr i64 %a0, 40
ret i64 %shr
}