Nadav Rotem 17b9d8cba2 Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target ... because it does not support CMOV of vectors. To implement this efficientlyi, we broadcast the condition bit and use a sequence of NAND-OR to select between the two operands. This is the same sequence we use for targets that don't have vector BLENDs (like SSE2). rdar://12201387 llvm-svn: 162926		2012-08-30 19:17:29 +00:00
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Analysis	llvm/test/Analysis/Profiling: Mark 3 of them as REQUIRES: loadable_module.	2012-08-29 00:37:46 +00:00
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CodeGen	Currently targets that do not support selects with scalar conditions and vector operands - scalarize the code. ARM is such a target	2012-08-30 19:17:29 +00:00
DebugInfo	Add basic support for .debug_ranges section to LLVM's DebugInfo library.	2012-08-27 07:17:47 +00:00
ExecutionEngine	Should put test case under test/ExecutionEngine/MCJIT/	2012-08-30 00:43:57 +00:00
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MC	The instruction DEXT may be transformed into DEXTU or DEXTM depending	2012-08-28 20:07:41 +00:00
Object	Create llvm/test/Object/Mips/lit.local.cfg to check Mips in targets_to_build.	2012-08-29 01:37:57 +00:00
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Transforms	Fix test case.	2012-08-30 15:42:45 +00:00
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CMakeLists.txt	llvm/test: [CMake] Add profile_rt-shared to deps.	2012-08-29 00:37:56 +00:00
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