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471bdf5106
Summary: Mem op clustering adds a weak edge in the DAG between two loads or stores that should be clustered, but the direction of this edge is pretty arbitrary (it depends on the sort order of MemOpInfo, which represents the operands of a load or store). This often means that two loads or stores will get reordered even if they would naturally have been scheduled together anyway, which leads to test case churn and goes against the scheduler's "do no harm" philosophy. The fix makes sure that the direction of the edge always matches the original code order of the instructions. Reviewers: atrick, MatzeB, arsenm, rampitec, t.p.northover Subscribers: jvesely, wdng, nhaehnle, kristof.beyls, hiraditya, javed.absar, arphaman, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D72706
62 lines
2.0 KiB
LLVM
62 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=aarch64-unknown-linux-gnu -O3 %s -o - | FileCheck %s
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define void @foo(i32 %In1, <2 x i128> %In2, <2 x i128> %In3, <2 x i128> *%Out) {
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; CHECK-LABEL: foo:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w8, w0, #0x1
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; CHECK-NEXT: fmov s0, wzr
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; CHECK-NEXT: fmov s1, w8
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; CHECK-NEXT: ldp x8, x9, [sp, #8]
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; CHECK-NEXT: ldr x10, [sp]
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; CHECK-NEXT: cmeq v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: fmov w11, s0
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; CHECK-NEXT: tst w11, #0x1
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; CHECK-NEXT: csel x11, x2, x6, ne
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; CHECK-NEXT: csel x12, x3, x7, ne
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; CHECK-NEXT: csel x10, x4, x10, ne
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; CHECK-NEXT: csel x8, x5, x8, ne
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; CHECK-NEXT: stp x10, x8, [x9, #16]
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; CHECK-NEXT: stp x11, x12, [x9]
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; CHECK-NEXT: ret
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%cond = and i32 %In1, 1
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%cbool = icmp eq i32 %cond, 0
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%res = select i1 %cbool, <2 x i128> %In2, <2 x i128> %In3
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store <2 x i128> %res, <2 x i128> *%Out
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ret void
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}
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; Check case when scalar size is not power of 2.
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define void @bar(i32 %In1, <2 x i96> %In2, <2 x i96> %In3, <2 x i96> *%Out) {
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; CHECK-LABEL: bar:
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; CHECK: // %bb.0:
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; CHECK-NEXT: and w9, w0, #0x1
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; CHECK-NEXT: fmov s0, wzr
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; CHECK-NEXT: fmov s1, w9
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; CHECK-NEXT: cmeq v0.4s, v1.4s, v0.4s
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; CHECK-NEXT: ldp x11, x8, [sp, #8]
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; CHECK-NEXT: ldr x10, [sp]
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; CHECK-NEXT: dup v1.4s, v0.s[0]
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; CHECK-NEXT: mov x9, v1.d[1]
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; CHECK-NEXT: lsr x9, x9, #32
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; CHECK-NEXT: tst w9, #0x1
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; CHECK-NEXT: fmov w9, s0
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; CHECK-NEXT: csel x11, x5, x11, ne
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; CHECK-NEXT: csel x10, x4, x10, ne
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; CHECK-NEXT: tst w9, #0x1
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; CHECK-NEXT: csel x9, x3, x7, ne
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; CHECK-NEXT: csel x12, x2, x6, ne
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; CHECK-NEXT: stur x10, [x8, #12]
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; CHECK-NEXT: str x12, [x8]
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; CHECK-NEXT: str w9, [x8, #8]
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; CHECK-NEXT: str w11, [x8, #20]
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; CHECK-NEXT: ret
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%cond = and i32 %In1, 1
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%cbool = icmp eq i32 %cond, 0
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%res = select i1 %cbool, <2 x i96> %In2, <2 x i96> %In3
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store <2 x i96> %res, <2 x i96> *%Out
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ret void
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}
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