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https://github.com/RPCS3/llvm-mirror.git
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0f6e08381a
Summary: Implements the following intrinsics: - @llvm.aarch64.sve.histcnt - @llvm.aarch64.sve.histseg - @llvm.aarch64.sve.match - @llvm.aarch64.sve.nmatch Reviewers: c-rhodes, sdesmalen, dancgr, efriedma, rengolin Reviewed By: c-rhodes Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D74117
55 lines
2.5 KiB
LLVM
55 lines
2.5 KiB
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2 -asm-verbose=0 < %s | FileCheck %s
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;
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; MATCH
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;
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define <vscale x 16 x i1> @match_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: match_i8:
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; CHECK: match p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 8 x i1> @match_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: match_i16:
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; CHECK: match p0.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.match.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i1> %out
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}
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;
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; NMATCH
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;
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define <vscale x 16 x i1> @nmatch_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) {
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; CHECK-LABEL: nmatch_i8:
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; CHECK: match p0.b, p0/z, z0.b, z1.b
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; CHECK-NEXT: ret
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%out = call <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1> %pg,
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<vscale x 16 x i8> %a,
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<vscale x 16 x i8> %b)
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ret <vscale x 16 x i1> %out
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}
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define <vscale x 8 x i1> @nmatch_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) {
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; CHECK-LABEL: nmatch_i16:
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; CHECK: match p0.h, p0/z, z0.h, z1.h
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; CHECK-NEXT: ret
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%out = call <vscale x 8 x i1> @llvm.aarch64.sve.nmatch.nxv8i16(<vscale x 8 x i1> %pg,
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<vscale x 8 x i16> %a,
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<vscale x 8 x i16> %b)
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ret <vscale x 8 x i1> %out
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}
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declare <vscale x 16 x i1> @llvm.aarch64.sve.match.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.match.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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declare <vscale x 16 x i1> @llvm.aarch64.sve.nmatch.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>)
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declare <vscale x 8 x i1> @llvm.aarch64.sve.nmatch.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>)
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