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Lei Liu 51c8520dd3 AArch64: Set shift bit of TLSLE HI12 add instruction

Summary: AArch64 LLVM assembler emits add instruction without shift bit to calculate the higher 12-bit address of TLS variables in local exec model.  This generates wrong code sequence to access TLS variables with thread offset larger than 0x1000.

Reviewers: t.p.northover, peter.smith, rovka

Subscribers: salim.nasser, aemerson, llvm-commits, rengolin

Differential Revision: https://reviews.llvm.org/D24702

llvm-svn: 282661

2016-09-29 01:05:48 +00:00

AArch64

AArch64: Set shift bit of TLSLE HI12 add instruction

2016-09-29 01:05:48 +00:00

AMDGPU

Revert "[AMDGPU] Disassembler: print label names in branch instructions"

2016-09-26 11:29:03 +00:00

ARM

Emit S_COMPILE3 CodeView record

2016-09-20 17:20:51 +00:00

AsmParser

[MC] Support .ds directives in assembler parser