Sjoerd Meijer c3b59a654a [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction
This adds the Armv8.4-A Trace synchronization barrier (TSB) instruction.

Differential Revision: https://reviews.llvm.org/D48918

llvm-svn: 336418
2018-07-06 08:03:12 +00:00
..
2017-12-21 11:17:49 +00:00
2017-12-21 11:17:49 +00:00
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