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dacbc9891d
This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
190 lines
5.2 KiB
ArmAsm
190 lines
5.2 KiB
ArmAsm
@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16 -show-encoding < %s 2>&1 | FileCheck %s
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@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+thumb-mode -show-encoding < %s 2>&1 | FileCheck %s
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vadd.f16 s0, s1, s0
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@ CHECK: instruction requires: full half-float
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vsub.f16 s0, s1, s0
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@ CHECK: instruction requires: full half-float
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vdiv.f16 s0, s1, s0
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@ CHECK: instruction requires: full half-float
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vmul.f16 s0, s1, s0
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@ CHECK: instruction requires: full half-float
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vnmul.f16 s0, s1, s0
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@ CHECK: instruction requires: full half-float
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vmla.f16 s1, s2, s0
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@ CHECK: instruction requires: full half-float
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vmls.f16 s1, s2, s0
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@ CHECK: instruction requires: full half-float
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vnmla.f16 s1, s2, s0
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@ CHECK: instruction requires: full half-float
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vnmls.f16 s1, s2, s0
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@ CHECK: instruction requires: full half-float
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vcmp.f16 s0, s1
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@ CHECK: instruction requires: full half-float
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vcmp.f16 s2, #0
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@ CHECK: instruction requires: full half-float
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vcmpe.f16 s1, s0
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@ CHECK: instruction requires: full half-float
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vcmpe.f16 s0, #0
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@ CHECK: instruction requires: full half-float
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vabs.f16 s0, s0
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@ CHECK: instruction requires: full half-float
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vneg.f16 s0, s0
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@ CHECK: instruction requires: full half-float
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vsqrt.f16 s0, s0
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@ CHECK: instruction requires: full half-float
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vcvt.f16.s32 s0, s0
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vcvt.f16.u32 s0, s0
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vcvt.s32.f16 s0, s0
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vcvt.u32.f16 s0, s0
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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vcvtr.s32.f16 s0, s1
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vcvtr.u32.f16 s0, s1
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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vcvt.f16.u32 s0, s0, #20
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vcvt.f16.u16 s0, s0, #1
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vcvt.f16.s32 s1, s1, #20
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vcvt.f16.s16 s17, s17, #1
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vcvt.u32.f16 s12, s12, #20
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vcvt.u16.f16 s28, s28, #1
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vcvt.s32.f16 s1, s1, #20
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vcvt.s16.f16 s17, s17, #1
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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vcvta.s32.f16 s2, s3
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@ CHECK: instruction requires: full half-float
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vcvtn.s32.f16 s6, s23
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@ CHECK: instruction requires: full half-float
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vcvtp.s32.f16 s0, s4
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@ CHECK: instruction requires: full half-float
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vcvtm.s32.f16 s17, s8
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@ CHECK: instruction requires: full half-float
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vcvta.u32.f16 s2, s3
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@ CHECK: instruction requires: full half-float
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vcvtn.u32.f16 s6, s23
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@ CHECK: instruction requires: full half-float
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vcvtp.u32.f16 s0, s4
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@ CHECK: instruction requires: full half-float
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vcvtm.u32.f16 s17, s8
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@ CHECK: instruction requires: full half-float
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vselge.f16 s4, s1, s23
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@ CHECK: instruction requires: full half-float
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vselgt.f16 s0, s1, s0
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@ CHECK: instruction requires: full half-float
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vseleq.f16 s30, s28, s23
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@ CHECK: instruction requires: full half-float
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vselvs.f16 s21, s16, s14
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@ CHECK: instruction requires: full half-float
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vmaxnm.f16 s5, s12, s0
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@ CHECK: instruction requires: full half-float
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vminnm.f16 s0, s0, s12
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@ CHECK: instruction requires: full half-float
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vrintz.f16 s3, s24
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@ CHECK: instruction requires: full half-float
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vrintr.f16 s0, s9
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@ CHECK: instruction requires: full half-float
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vrintx.f16 s10, s14
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@ CHECK: instruction requires: full half-float
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vrinta.f16 s12, s1
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@ CHECK: instruction requires: full half-float
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vrintn.f16 s12, s1
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@ CHECK: instruction requires: full half-float
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vrintp.f16 s12, s1
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@ CHECK: instruction requires: full half-float
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vrintm.f16 s12, s1
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@ CHECK: instruction requires: full half-float
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vfma.f16 s2, s7, s4
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@ CHECK: instruction requires: full half-float
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vfms.f16 s2, s7, s4
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@ CHECK: instruction requires: full half-float
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vfnma.f16 s2, s7, s4
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@ CHECK: instruction requires: full half-float
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vfnms.f16 s2, s7, s4
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@ CHECK: instruction requires: full half-float
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vmovx.f16 s2, s5
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vins.f16 s2, s5
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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vldr.16 s1, [pc, #6]
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vldr.16 s2, [pc, #510]
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vldr.16 s3, [pc, #-510]
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vldr.16 s4, [r4, #-18]
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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vstr.16 s1, [pc, #6]
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vstr.16 s2, [pc, #510]
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vstr.16 s3, [pc, #-510]
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vstr.16 s4, [r4, #-18]
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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vmov.f16 s0, #1.0
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@ CHECK: instruction requires: full half-float
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vmov.f16 s1, r2
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vmov.f16 r3, s4
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@ CHECK: instruction requires: full half-float
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@ CHECK: instruction requires: full half-float
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