llvm-mirror/lib/CodeGen
Evan Cheng 1732a41371 Really turn if-converter loose:
1. Consider all possible ifcvt cases at once. No longer restricted to bottom
   up iterative approach.
2. Sort all possible cases based on a cost function. Perform the most profitable
   ones first invalidate others that target the same blocks.
3. Fixed a number of bugs related to block duplication.

llvm-svn: 37613
2007-06-16 09:34:52 +00:00
..
SelectionDAG Codegen support (stripped out) for the annotate attribute. 2007-06-15 22:26:58 +00:00
AsmPrinter.cpp Global ctors / dtors alignment shouldn't be hard-coded at 4. e.g. It could be 8 for 64-bit targets. 2007-06-04 20:39:18 +00:00
BranchFolding.cpp Make throttle a hidden parameter, per review. 2007-06-08 01:08:52 +00:00
DwarfWriter.cpp Use more realistically sized vectors. Reserve capacity if we know in advance 2007-06-08 08:59:11 +00:00
ELFWriter.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
ELFWriter.h Drop 'const' 2007-05-03 01:11:54 +00:00
IfConversion.cpp Really turn if-converter loose: 2007-06-16 09:34:52 +00:00
IntrinsicLowering.cpp Codegen support (stripped out) for the annotate attribute. 2007-06-15 22:26:58 +00:00
LiveInterval.cpp Add a register allocation preference field; add a method to compute size of a live interval. 2007-04-17 20:25:11 +00:00
LiveIntervalAnalysis.cpp Add a target hook to allow loads from constant pools to be rematerialized, and an 2007-06-14 20:50:44 +00:00
LiveVariables.cpp When marking a register as being implicitly defined, make sure to clear its partial use info as well. 2007-05-14 20:39:18 +00:00
LLVMTargetMachine.cpp name change requested by review of previous patch 2007-05-22 18:31:04 +00:00
MachineBasicBlock.cpp Move ReplaceUsesOfBlockWith() out of BranchFolding into a MachineBasicBlock general facility. 2007-06-04 06:44:01 +00:00
MachineFunction.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
MachineInstr.cpp MachineInstr::isPredicable() is no longer needed. 2007-06-15 19:06:07 +00:00
MachineModuleInfo.cpp The semantics of invoke require that we always jump to the unwind block 2007-06-02 17:16:06 +00:00
MachinePassRegistry.cpp
MachOWriter.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
MachOWriter.h Drop 'const' 2007-05-03 01:11:54 +00:00
Makefile
Passes.cpp
PHIElimination.cpp Fix typo in comment. 2007-05-06 13:37:16 +00:00
PhysRegTracker.h
PrologEpilogInserter.cpp Fix PR1424. 2007-05-31 18:27:58 +00:00
README.txt Fancier algorithm in tail-merge comment implemented, so remove comment. 2007-06-01 23:04:28 +00:00
RegAllocLinearScan.cpp Factor live variable analysis so it does not do register coalescing 2007-06-08 17:18:56 +00:00
RegAllocLocal.cpp Change names from RA to something unique to get rid of naming conflicts with 2007-05-08 19:02:46 +00:00
RegAllocSimple.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
RegisterScavenging.cpp If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames. 2007-05-01 09:01:42 +00:00
SimpleRegisterCoalescing.cpp Factor live variable analysis so it does not do register coalescing 2007-06-08 17:18:56 +00:00
TwoAddressInstructionPass.cpp Fix typo in comment. 2007-05-06 13:37:16 +00:00
UnreachableBlockElim.cpp Fix typo in comment. 2007-05-06 13:37:16 +00:00
VirtRegMap.cpp Add a target hook to allow loads from constant pools to be rematerialized, and an 2007-06-14 20:50:44 +00:00
VirtRegMap.h Re-materialize all loads from fixed stack slots. 2007-04-04 07:40:01 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]
//===---------------------------------------------------------------------===//