Dmitry Preobrazhensky 77393a5f25 [AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16 ...

See bug 33629: https://bugs.llvm.org//show_bug.cgi?id=33629

Reviewers: artem.tamazov, SamWot, arsenm

Differential Revision: https://reviews.llvm.org/D39488

llvm-svn: 318955

2017-11-24 15:37:14 +00:00

..

AArch64

[AArch64][TableGen] Skip tied result operands for InstAlias

2017-11-20 14:36:40 +00:00

AMDGPU

[AMDGPU][MC][GFX9] Added v_interp_p2_f16 and v_interp_p2_legacy_f16

2017-11-24 15:37:14 +00:00

ARC

[ARC] Add ARC backend.

2017-08-24 15:40:33 +00:00

ARM

[ARM] Fix disassembly for conditional VMRS and VMSR instructions in ARM mode

2017-10-18 14:47:37 +00:00

Hexagon

[Hexagon] Remove trailing spaces, NFC

2017-11-22 20:43:00 +00:00

Lanai

[lanai] Add Lanai backend.

2016-03-28 13:09:54 +00:00

Mips

Reland "[mips][mt][6/7] Add support for mftr, mttr instructions."

2017-11-14 22:26:42 +00:00

PowerPC

[Power9] Add missing Power9 instructions.

2017-09-19 15:22:36 +00:00

Sparc

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

2016-03-09 18:20:21 +00:00

SystemZ

[SystemZ] Add support for IBM z14 processor (3/3)

2017-07-17 17:44:20 +00:00

X86

Avoid unecessary opsize byte in segment move to memory

2017-11-21 19:28:13 +00:00

XCore

Reduce verbiage of lit.local.cfg files

2014-06-09 22:42:55 +00:00