Hsiangkai Wang 8937023816 [RISCV] Add CFI directives for RISCV prologue/epilog. ... In order to generate correct debug frame information, it needs to generate CFI information in prologue and epilog. Differential Revision: https://reviews.llvm.org/D61773 llvm-svn: 363120		2019-06-12 03:04:22 +00:00
..
AsmParser	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
Disassembler	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
MCTargetDesc	[RISCV] Add CFI directives for RISCV prologue/epilog.	2019-06-12 03:04:22 +00:00
TargetInfo	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
Utils	[RISCV] Add lowering of addressing sequences for PIC	2019-06-11 12:57:47 +00:00
CMakeLists.txt	[RISCV] Move InstPrinter files to MCTargetDesc. NFC	2019-05-11 02:43:58 +00:00
LLVMBuild.txt	[RISCV] Move InstPrinter files to MCTargetDesc. NFC	2019-05-11 02:43:58 +00:00
RISCV.h
RISCV.td	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVAsmPrinter.cpp	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
RISCVCallingConv.td	[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs	2019-03-30 17:59:30 +00:00
RISCVExpandPseudoInsts.cpp	[RISCV] Add lowering of addressing sequences for PIC	2019-06-11 12:57:47 +00:00
RISCVFrameLowering.cpp	[RISCV] Add CFI directives for RISCV prologue/epilog.	2019-06-12 03:04:22 +00:00
RISCVFrameLowering.h
RISCVInstrFormats.td	[RISCV] Implement pseudo instructions for load/store from a symbol address.	2019-02-20 03:31:32 +00:00
RISCVInstrFormatsC.td
RISCVInstrInfo.cpp	[RISCV] Add lowering of addressing sequences for PIC	2019-06-11 12:57:47 +00:00
RISCVInstrInfo.h	Reapply: [RISCV] Set isAsCheapAsAMove for ADDI, ORI, XORI, LUI	2019-01-25 20:22:49 +00:00
RISCVInstrInfo.td	[RISCV] Support assembling TLS LA pseudo instructions	2019-05-23 14:46:27 +00:00
RISCVInstrInfoA.td
RISCVInstrInfoC.td	[RISCV] Add implied zero offset load/store alias patterns	2019-02-21 14:09:34 +00:00
RISCVInstrInfoD.td	[RISCV] Add seto pattern expansion	2019-04-01 09:54:14 +00:00
RISCVInstrInfoF.td	[RISCV] Add seto pattern expansion	2019-04-01 09:54:14 +00:00
RISCVInstrInfoM.td	[RISCV] Custom-legalise i32 SDIV/UDIV/UREM on RV64M	2019-01-25 05:11:34 +00:00
RISCVISelDAGToDAG.cpp
RISCVISelLowering.cpp	[RISCV] Add lowering of addressing sequences for PIC	2019-06-11 12:57:47 +00:00
RISCVISelLowering.h	[RISCV] Add lowering of addressing sequences for PIC	2019-06-11 12:57:47 +00:00
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp	[RISCV] Add lowering of addressing sequences for PIC	2019-06-11 12:57:47 +00:00
RISCVMergeBaseOffset.cpp
RISCVRegisterInfo.cpp	[RISCV] Add codegen support for ilp32f, ilp32d, lp64f, and lp64d ("hard float") ABIs	2019-03-30 17:59:30 +00:00
RISCVRegisterInfo.h
RISCVRegisterInfo.td	[RISCV] Allow fp as an alias of s0	2019-03-11 21:35:26 +00:00
RISCVSubtarget.cpp	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVSubtarget.h	[RISCV] Add basic RV32E definitions and MC layer support	2019-03-22 11:21:40 +00:00
RISCVSystemOperands.td	[RISCV] Allow access to FP CSRs without F extension	2019-03-08 23:01:08 +00:00
RISCVTargetMachine.cpp	Revert CMake: Make most target symbols hidden by default	2019-06-11 03:21:13 +00:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00
RISCVTargetObjectFile.h	[RISCV] Put data smaller than eight bytes to small data section	2019-04-11 04:59:13 +00:00