Jan Vesely 523782f6c1 AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodes ... This will make transition to SCRATCH_MEMORY easier Differential Revision: https://reviews.llvm.org/D24746 llvm-svn: 291279		2017-01-06 21:00:46 +00:00
..
AArch64	AArch64CollectLOH: Rewrite as block-local analysis.	2017-01-06 19:22:01 +00:00
AMDGPU	AMDGPU/R600: Don't use REGISTER_{LOAD,STORE} ISD nodes	2017-01-06 21:00:46 +00:00
ARM	Emit .cfi_sections before the first .cfi_startproc	2017-01-02 18:05:27 +00:00
AVR	[AVR] Optimize 16-bit ANDs with '1'	2016-12-31 01:07:14 +00:00
BPF
Generic	PR 31534: When emitting both DWARF unwind tables and debug information,	2017-01-05 20:55:28 +00:00
Hexagon	Fix two bugs in the pipeliner in renaming phis in the prolog and epilog	2016-12-22 18:49:55 +00:00
Inputs
Lanai
Mips	[mips] Fix compact branch hazard detection, part 2	2016-12-22 19:29:50 +00:00
MIR	[AArch64] Fold some filled/spilled subreg COPYs	2017-01-05 21:51:42 +00:00
MSP430
NVPTX	[SelectionDAG] Correctly transform range metadata to AssertZExt	2017-01-06 00:11:46 +00:00
PowerPC	[Legalizer] Fix fp-to-uint to fp-tosint promotion assertion.	2017-01-04 22:11:42 +00:00
SPARC	[SPARC] Fix test so that it checks the correct label.	2017-01-04 14:01:58 +00:00
SystemZ
Thumb
Thumb2	Make the canonicalisation on shifts benifit to more case.	2016-12-23 02:56:07 +00:00
WebAssembly
WinEH
X86	[X86][SSE] Standardized triples in vector shift tests	2017-01-06 19:56:57 +00:00
XCore