mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-12-05 10:17:36 +00:00
993081c749
Summary: Make AArch64InstrInfo::foldMemoryOperandImpl more general by folding all full COPYs between register classes of the same size that are either spilled or refilled. Reviewers: MatzeB, qcolombet Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27271 llvm-svn: 288439
31 lines
758 B
LLVM
31 lines
758 B
LLVM
; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-linux-gnu | FileCheck %s
|
|
|
|
@var32 = global i32 0
|
|
@var64 = global i64 0
|
|
|
|
define void @test_zr() {
|
|
; CHECK-LABEL: test_zr:
|
|
|
|
store i32 0, i32* @var32
|
|
; CHECK: str wzr, [{{x[0-9]+}}, {{#?}}:lo12:var32]
|
|
store i64 0, i64* @var64
|
|
; CHECK: str xzr, [{{x[0-9]+}}, {{#?}}:lo12:var64]
|
|
|
|
ret void
|
|
; CHECK: ret
|
|
}
|
|
|
|
define void @test_sp(i32 %val) {
|
|
; CHECK-LABEL: test_sp:
|
|
|
|
; Important correctness point here is that LLVM doesn't try to use xzr
|
|
; as an addressing register: "str w0, [xzr]" is not a valid A64
|
|
; instruction (0b11111 in the Rn field would mean "sp").
|
|
%addr = getelementptr i32, i32* null, i64 0
|
|
store i32 %val, i32* %addr
|
|
; CHECK: str {{w[0-9]+}}, [{{x[0-9]+|sp}}]
|
|
|
|
ret void
|
|
; CHECK: ret
|
|
}
|