llvm-mirror/lib/CodeGen
2007-05-16 12:12:23 +00:00
..
SelectionDAG Use a ptr set instead of a linear search to unique TokenFactor operands. 2007-05-16 06:37:59 +00:00
AsmPrinter.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
BranchFolding.cpp Remove extra CFG edges before doing these passes; it makes them happier. 2007-05-15 21:19:17 +00:00
DwarfWriter.cpp Output exception call-sites in address order, as required by the unwinding 2007-05-16 12:12:23 +00:00
ELFWriter.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
ELFWriter.h Drop 'const' 2007-05-03 01:11:54 +00:00
IfConversion.cpp Devang points out that we need an assertion here. 2007-05-16 05:11:10 +00:00
IntrinsicLowering.cpp Un-brain-dead-ify the lowering of part set for the reverse case. 2007-05-15 02:26:52 +00:00
LiveInterval.cpp Add a register allocation preference field; add a method to compute size of a live interval. 2007-04-17 20:25:11 +00:00
LiveIntervalAnalysis.cpp Only worry about intervening kill if there are more than one live ranges in the interval. 2007-05-14 21:23:51 +00:00
LiveVariables.cpp When marking a register as being implicitly defined, make sure to clear its partial use info as well. 2007-05-14 20:39:18 +00:00
LLVMTargetMachine.cpp move a bunch of code out of the sdisel pass into its own opt pass "codegenprepare". 2007-03-31 04:18:03 +00:00
MachineBasicBlock.cpp print isLandingPad() for MBBs 2007-04-30 23:12:53 +00:00
MachineFunction.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
MachineInstr.cpp Added getNumExplicitOperands and findFirstPredOperand. 2007-05-15 01:26:09 +00:00
MachineModuleInfo.cpp Emit multiple common EH frames for multiple (including blank) personality 2007-05-13 15:42:26 +00:00
MachinePassRegistry.cpp
MachOWriter.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
MachOWriter.h Drop 'const' 2007-05-03 01:11:54 +00:00
Makefile
Passes.cpp
PHIElimination.cpp Fix typo in comment. 2007-05-06 13:37:16 +00:00
PhysRegTracker.h
PrologEpilogInserter.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
README.txt Updates. 2007-04-30 18:42:09 +00:00
RegAllocLinearScan.cpp Change names from RA to something unique to get rid of naming conflicts with 2007-05-08 19:02:46 +00:00
RegAllocLocal.cpp Change names from RA to something unique to get rid of naming conflicts with 2007-05-08 19:02:46 +00:00
RegAllocSimple.cpp Drop 'const' 2007-05-03 01:11:54 +00:00
RegisterScavenging.cpp If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames. 2007-05-01 09:01:42 +00:00
TwoAddressInstructionPass.cpp Fix typo in comment. 2007-05-06 13:37:16 +00:00
UnreachableBlockElim.cpp Fix typo in comment. 2007-05-06 13:37:16 +00:00
VirtRegMap.cpp Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 2007-04-26 19:00:32 +00:00
VirtRegMap.h Re-materialize all loads from fixed stack slots. 2007-04-04 07:40:01 +00:00

//===---------------------------------------------------------------------===//

Common register allocation / spilling problem:

        mul lr, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        ldr r4, [sp, #+52]
        mla r4, r3, lr, r4

can be:

        mul lr, r4, lr
        mov r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

and then "merge" mul and mov:

        mul r4, r4, lr
        str lr, [sp, #+52]
        ldr lr, [r1, #+32]
        sxth r3, r3
        mla r4, r3, lr, r4

It also increase the likelyhood the store may become dead.

//===---------------------------------------------------------------------===//

I think we should have a "hasSideEffects" flag (which is automatically set for
stuff that "isLoad" "isCall" etc), and the remat pass should eventually be able
to remat any instruction that has no side effects, if it can handle it and if
profitable.

For now, I'd suggest having the remat stuff work like this:

1. I need to spill/reload this thing.
2. Check to see if it has side effects.
3. Check to see if it is simple enough: e.g. it only has one register
destination and no register input.
4. If so, clone the instruction, do the xform, etc.

Advantages of this are:

1. the .td file describes the behavior of the instructions, not the way the
   algorithm should work.
2. as remat gets smarter in the future, we shouldn't have to be changing the .td
   files.
3. it is easier to explain what the flag means in the .td file, because you
   don't have to pull in the explanation of how the current remat algo works.

Some potential added complexities:

1. Some instructions have to be glued to it's predecessor or successor. All of
   the PC relative instructions and condition code setting instruction. We could
   mark them as hasSideEffects, but that's not quite right. PC relative loads
   from constantpools can be remat'ed, for example. But it requires more than
   just cloning the instruction. Some instructions can be remat'ed but it
   expands to more than one instruction. But allocator will have to make a
   decision.

4. As stated in 3, not as simple as cloning in some cases. The target will have
   to decide how to remat it. For example, an ARM 2-piece constant generation
   instruction is remat'ed as a load from constantpool.

//===---------------------------------------------------------------------===//

bb27 ...
        ...
        %reg1037 = ADDri %reg1039, 1
        %reg1038 = ADDrs %reg1032, %reg1039, %NOREG, 10
    Successors according to CFG: 0x8b03bf0 (#5)

bb76 (0x8b03bf0, LLVM BB @0x8b032d0, ID#5):
    Predecessors according to CFG: 0x8b0c5f0 (#3) 0x8b0a7c0 (#4)
        %reg1039 = PHI %reg1070, mbb<bb76.outer,0x8b0c5f0>, %reg1037, mbb<bb27,0x8b0a7c0>

Note ADDri is not a two-address instruction. However, its result %reg1037 is an
operand of the PHI node in bb76 and its operand %reg1039 is the result of the
PHI node. We should treat it as a two-address code and make sure the ADDri is
scheduled after any node that reads %reg1039.

//===---------------------------------------------------------------------===//

Use local info (i.e. register scavenger) to assign it a free register to allow
reuse:
	ldr r3, [sp, #+4]
	add r3, r3, #3
	ldr r2, [sp, #+8]
	add r2, r2, #2
	ldr r1, [sp, #+4]  <==
	add r1, r1, #1
	ldr r0, [sp, #+4]
	add r0, r0, #2

//===---------------------------------------------------------------------===//

LLVM aggressively lift CSE out of loop. Sometimes this can be negative side-
effects:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
load [i + R1]
...
load [i + R2]
...
load [i + R3]

Suppose there is high register pressure, R1, R2, R3, can be spilled. We need
to implement proper re-materialization to handle this:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
R1 = X + 4  @ re-materialized
load [i + R1]
...
R2 = X + 7 @ re-materialized
load [i + R2]
...
R3 = X + 15 @ re-materialized
load [i + R3]

Furthermore, with re-association, we can enable sharing:

R1 = X + 4
R2 = X + 7
R3 = X + 15

loop:
T = i + X
load [T + 4]
...
load [T + 7]
...
load [T + 15]