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llvm-mirror/lib/Target/R600
History
Vincent Lejeune 8a53bf61f4 R600: Fix an unitialized variable in R600InstrInfo.cpp 
llvm-svn: 185294
2013-06-30 21:44:06 +00:00
..
InstPrinter
R600: Bank Swizzle now display SCL equivalent
2013-06-29 19:32:29 +00:00
MCTargetDesc
R600: Use correct encoding for Vertex Fetch instructions on Cayman
2013-06-14 22:12:30 +00:00
TargetInfo
R600: Remove unnecessary include
2013-06-07 20:28:43 +00:00
AMDGPU.h
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDGPU.td
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDGPUAsmPrinter.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUAsmPrinter.h
R600: Emit used GPRs count
2013-04-17 15:17:25 +00:00
AMDGPUCallingConv.td
R600/SI: Add support for v4i32 and v4f32 kernel args
2013-06-25 02:39:25 +00:00
AMDGPUConvertToISA.cpp
…
AMDGPUFrameLowering.cpp
R600: Fix calculation of stack offset in AMDGPUFrameLowering
2013-06-07 20:52:05 +00:00
AMDGPUFrameLowering.h
R600: Support for indirect addressing v4
2013-02-06 17:32:29 +00:00
AMDGPUIndirectAddressing.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
AMDGPUInstrInfo.cpp
R600: Use new getNamedOperandIdx function generated by TableGen
2013-06-25 21:22:18 +00:00
AMDGPUInstrInfo.h
R600: Use new getNamedOperandIdx function generated by TableGen
2013-06-25 21:22:18 +00:00
AMDGPUInstrInfo.td
Create an FPOW SDNode opcode def in the target independent .td file rather than in a specific backend.
2013-05-22 06:36:09 +00:00
AMDGPUInstructions.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUIntrinsics.td
R600: Add support for GROUP_BARRIER instruction
2013-06-28 15:46:59 +00:00
AMDGPUISelLowering.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUISelLowering.h
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUMachineFunction.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUMachineFunction.h
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDGPUMCInstLower.cpp
Move all of the header files which are involved in modelling the LLVM IR
2013-01-02 11:36:10 +00:00
AMDGPUMCInstLower.h
R600: BB operand support for SI
2012-12-17 15:14:54 +00:00
AMDGPURegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
AMDGPURegisterInfo.td
Make SubRegIndex size mandatory, following r183020.
2013-05-31 23:45:26 +00:00
AMDGPUSubtarget.cpp
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDGPUSubtarget.h
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDGPUTargetMachine.cpp
Move StructurizeCFG out of R600 to generic Transforms.
2013-06-19 20:18:24 +00:00
AMDGPUTargetMachine.h
Remove dead prototype.
2013-06-18 06:24:14 +00:00
AMDILBase.td
R600: Move Subtarget feature definitions into AMDGPU.td
2013-06-07 20:28:49 +00:00
AMDILCFGStructurizer.cpp
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDILInstrInfo.td
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDILIntrinsicInfo.cpp
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDILIntrinsicInfo.h
Move all of the header files which are involved in modelling the LLVM IR
2013-01-02 11:36:10 +00:00
AMDILIntrinsics.td
R600/SI: Use MULADD_IEEE/V_MAD_F32 instruction for mad pattern
2013-02-18 14:11:28 +00:00
AMDILISelDAGToDAG.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
AMDILISelLowering.cpp
R600: Rework subtarget info and remove AMDILDevice classes
2013-06-07 20:37:48 +00:00
AMDILRegisterInfo.td
…
CMakeLists.txt
Move StructurizeCFG out of R600 to generic Transforms.
2013-06-19 20:18:24 +00:00
LLVMBuild.txt
…
Makefile
…
Processors.td
R600/SI: Add processor types for each CIK variant
2013-06-28 20:23:29 +00:00
R600ControlFlowFinalizer.cpp
R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman
2013-06-14 22:12:24 +00:00
R600Defines.h
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600EmitClauseMarkers.cpp
R600: Add support for GROUP_BARRIER instruction
2013-06-28 15:46:59 +00:00
R600ExpandSpecialInstrs.cpp
R600: Use new getNamedOperandIdx function generated by TableGen
2013-06-25 21:22:18 +00:00
R600InstrFormats.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600InstrInfo.cpp
R600: Fix an unitialized variable in R600InstrInfo.cpp
2013-06-30 21:44:06 +00:00
R600InstrInfo.h
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600Instructions.td
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600Intrinsics.td
R600: Improve texture handling
2013-05-17 16:50:20 +00:00
R600ISelLowering.cpp
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600ISelLowering.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
R600MachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
R600MachineFunctionInfo.h
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
R600MachineScheduler.cpp
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600MachineScheduler.h
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600OptimizeVectorRegisters.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
R600Packetizer.cpp
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600RegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
R600RegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
R600RegisterInfo.td
R600: Support schedule and packetization of trans-only inst
2013-06-29 19:32:43 +00:00
R600Schedule.td
R600: Add local memory support via LDS
2013-06-28 15:47:08 +00:00
R600TextureIntrinsicsReplacer.cpp
Move passes from namespace llvm into anonymous namespaces. Sort includes while there.
2013-05-23 17:10:37 +00:00
SIAnnotateControlFlow.cpp
R600: Remove unnecessary include
2013-06-07 20:28:43 +00:00
SIDefines.h
R600/SI: Emit config values in register value pairs.
2013-04-15 17:51:35 +00:00
SIInsertWaits.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIInstrFormats.td
R600/SI: Use the same names for VOP3 operands and encoding fields
2013-05-20 15:02:08 +00:00
SIInstrInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIInstrInfo.h
R600/SI: adjust writemask to only the used components
2013-04-10 08:39:08 +00:00
SIInstrInfo.td
Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change.
2013-06-19 21:36:55 +00:00
SIInstructions.td
R600: Add SI load support for v[24]i32 and store for v2i32
2013-06-15 00:09:31 +00:00
SIIntrinsics.td
R600/SI: Add intrinsic for MIMG IMAGE_GET_RESINFO opcode
2013-05-06 23:02:19 +00:00
SIISelLowering.cpp
R600: Consolidate expansion of v2i32/v4i32 ops for EG/SI
2013-06-25 13:55:57 +00:00
SIISelLowering.h
R600/SI: Report unaligned memory accesses as legal for > 32-bit types
2013-06-25 02:39:35 +00:00
SILowerControlFlow.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIMachineFunctionInfo.cpp
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIMachineFunctionInfo.h
R600/SI: Share code recording ShaderTypeAttribute between generations
2013-04-01 21:47:53 +00:00
SIRegisterInfo.cpp
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIRegisterInfo.h
Don't cache the instruction and register info from the TargetMachine, because
2013-06-07 20:28:55 +00:00
SIRegisterInfo.td
R600/SI: dynamical figure out the reg class of MIMG
2013-04-10 08:39:16 +00:00
SISchedule.td
…