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cbce5f6883
llvm-mirror/test/MC
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Sander de Smalen cbce5f6883 [AArch64][SVE] Asm: Support for UZP and TRN instructions. 
This patch adds support for:
  UZP1  Concatenate even elements from two vectors
  UZP2  Concatenate  odd elements from two vectors
  TRN1  Interleave  even elements from two vectors
  TRN2  Interleave   odd elements from two vectors

With variants for both data and predicate vectors, e.g.
  uzp1    z0.b, z1.b, z2.b
  trn2    p0.s, p1.s, p2.s

llvm-svn: 336531
2018-07-09 09:12:17 +00:00
..
AArch64 [AArch64][SVE] Asm: Support for UZP and TRN instructions. 2018-07-09 09:12:17 +00:00
AMDGPU [AMDGPU] Fix lit failures introduced in r335281 2018-06-21 22:30:09 +00:00
ARM [AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction 2018-07-06 08:03:12 +00:00
AsmParser [X86] Fix test/MC/AsmParser/exprs-invalid.s after rL336104 2018-07-02 14:13:27 +00:00
AVR [AVR] Implement some missing code paths 2017-12-11 11:01:27 +00:00
BPF bpf: New disassembler testcases for 32-bit subregister support 2018-02-23 23:49:35 +00:00
COFF [CodeView] Add prefix to CodeView registers. 2018-05-29 14:35:34 +00:00
Disassembler [AArch64] Armv8.4-A: TLB support 2018-07-06 13:00:16 +00:00
ELF Replace unused output filenames with /dev/null in tests 2018-07-02 18:16:44 +00:00
Hexagon [Hexagon] Fix the value of HexagonII::TypeCVI_FIRST 2018-06-19 18:09:54 +00:00
Lanai
MachO [MC] Error on a .zerofill directive in a non-virtual section 2018-07-02 17:29:43 +00:00
Mips [mips] Correct predicates for loads, bit manipulation instructions and some pseudos 2018-06-20 19:59:58 +00:00
PowerPC [PowerPC] Fix incorrectly encoded wait instruction 2018-06-25 19:28:27 +00:00
RISCV [RISCV] Tail calls don't need to save return address 2018-06-21 14:37:09 +00:00
Sparc [Sparc] Add support for 13-bit PIC 2018-06-11 05:50:08 +00:00
SystemZ [SystemZ, AsmParser] Enable the mnemonic spell corrector. 2017-07-18 09:17:00 +00:00
WebAssembly [WebAssembly] Ignore explicit section names for functions 2018-06-14 18:48:19 +00:00
X86 [X86][AsmParser] Don't consider %eip as a valid register outside of 32-bit mode. 2018-07-03 17:40:51 +00:00