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
This patch introduces a new instruction stage named 'IS_PENDING'. An instruction transitions from the IS_DISPATCHED to the IS_PENDING stage if input registers are not available, but their latency is known. This patch also adds a new set of instructions named 'PendingSet' to class Scheduler. The idea is that the PendingSet will only contain instructions that have reached the IS_PENDING stage. By construction, an instruction in the PendingSet is only dependent on instructions that have already reached the execution stage. The plan is to use this knowledge to identify bottlenecks caused by data dependencies (see PR37494). Differential Revision: https://reviews.llvm.org/D58066 llvm-svn: 353937
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