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https://github.com/RPCS3/llvm-mirror.git
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befddf9028
Summary: Enable hoisting and merging m0 defs that are initialized with the same immediate value. Fixes bug where removed instructions are not considered to interfere with other inits, and make sure to not hoist inits before block prologues. Reviewers: rampitec, arsenm Reviewed By: rampitec Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D64766 llvm-svn: 366135
226 lines
5.4 KiB
YAML
226 lines
5.4 KiB
YAML
# RUN: llc -march=amdgcn -amdgpu-enable-merge-m0 -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.1:
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# GCN: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.2:
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# GCN: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.3:
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# GCN: SI_INIT_M0 3
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# GCN: bb.4:
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# GCN-NOT: SI_INIT_M0
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# GCN: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 4
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.5:
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# GCN-NOT: SI_INIT_M0
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# GCN: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 4
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# GCN-NEXT: DS_WRITE_B32
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# GCN: bb.6:
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# GCN: SI_INIT_M0 -1,
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# GCN-NEXT: DS_WRITE_B32
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# GCN: SI_INIT_M0 %2
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 %2
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# GCN-NEXT: DS_WRITE_B32
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# GCN-NEXT: SI_INIT_M0 -1
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# GCN-NEXT: DS_WRITE_B32
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---
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name: merge-m0-many-init
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: sreg_32_xm0 }
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.2
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.2
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bb.2:
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successors: %bb.3
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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successors: %bb.4, %bb.5
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S_CBRANCH_VCCZ %bb.4, implicit undef $vcc
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S_BRANCH %bb.5
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bb.4:
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successors: %bb.6
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SI_INIT_M0 3, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 4, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.6
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bb.5:
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successors: %bb.6
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SI_INIT_M0 3, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 4, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.6
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bb.6:
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successors: %bb.0.entry, %bb.6
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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%2 = IMPLICIT_DEF
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SI_INIT_M0 %2, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 %2, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.6, implicit undef $vcc
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S_BRANCH %bb.0.entry
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...
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# GCN: bb.0.entry:
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# GCN: SI_INIT_M0 65536
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# GCN-NEXT: DS_WRITE_B32
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#GCN: bb.1:
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#GCN-NOT: SI_INIT_M0 65536
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#GCN-NOT: SI_INIT_M0 -1
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#GCN: bb.2:
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#GCN: SI_INIT_M0 -1
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#GCN: bb.3:
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#GCN: SI_INIT_M0 -1
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---
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name: merge-m0-dont-hoist-past-init-with-different-initializer
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.1
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bb.1:
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successors: %bb.2, %bb.3
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SI_INIT_M0 65536, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_CBRANCH_VCCZ %bb.2, implicit undef $vcc
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.4
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.4
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bb.3:
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successors: %bb.4
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.4
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bb.4:
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S_ENDPGM 0
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...
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# GCN: bb.0.entry:
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# GCN-NOT: SI_INIT_M0
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# GCN: S_OR_B64
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# GCN-NEXT: SI_INIT_M0
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#GCN: bb.1:
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#GCN-NOT: SI_INIT_M0 -1
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#GCN: bb.2:
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#GCN-NOT: SI_INIT_MO -1
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---
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name: merge-m0-after-prologue
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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body: |
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bb.0.entry:
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successors: %bb.1, %bb.2
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liveins: $sgpr0_sgpr1
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$exec = S_OR_B64 $exec, killed $sgpr0_sgpr1, implicit-def $scc
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%0 = IMPLICIT_DEF
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%1 = IMPLICIT_DEF
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S_CBRANCH_VCCZ %bb.1, implicit undef $vcc
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S_BRANCH %bb.2
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bb.1:
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successors: %bb.3
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.2:
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successors: %bb.3
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SI_INIT_M0 -1, implicit-def $m0
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DS_WRITE_B32 %0, %1, 0, 0, implicit $m0, implicit $exec
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S_BRANCH %bb.3
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bb.3:
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S_ENDPGM 0
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...
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