..
GlobalISel
[GlobalISel]: Fix lowering of G_Shuffle_vector where we pick up the wrong source index
2019-08-14 01:23:33 +00:00
32-bit-local-address-space.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
accvgpr-copy.mir
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
add3.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
add_i1.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
add_i64.ll
add_i128.ll
add_shl.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
add-debug.ll
add.i16.ll
add.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
add.v2i16.ll
AMDGPU: Undo sub x, c canonicalization for v2i16
2019-06-19 23:37:43 +00:00
addrspacecast-captured.ll
addrspacecast-constantexpr.ll
[FunctionAttrs] Annotate "willreturn" for intrinsics
2019-07-28 06:09:56 +00:00
addrspacecast.ll
adjust-writemask-invalid-copy.ll
agpr-register-count.ll
[AMDGPU] use v32f32 for 3 mfma intrinsics
2019-07-12 22:42:01 +00:00
alignbit-pat.ll
alloca.ll
always-uniform.ll
amdgcn-ieee.ll
amdgcn.bitcast.ll
amdgcn.private-memory.ll
amdgpu-alias-analysis.ll
AMDGPU: Improve alias analysis for GDS
2019-07-17 11:22:19 +00:00
amdgpu-codegenprepare-fdiv.ll
amdgpu-codegenprepare-i16-to-i32.ll
amdgpu-codegenprepare-idiv.ll
amdgpu-codegenprepare-mul24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
amdgpu-function-calls-option.ll
amdgpu-inline.ll
[AMDGPU] Tune inlining parameters for AMDGPU target
2019-07-17 16:51:29 +00:00
amdgpu-shader-calling-convention.ll
amdgpu.private-memory.ll
amdgpu.work-item-intrinsics.deprecated.ll
amdhsa-trap-num-sgprs.ll
amdpal_scratch_mergedshader.ll
amdpal-cs.ll
amdpal-es.ll
amdpal-gs.ll
amdpal-hs.ll
amdpal-ls.ll
amdpal-msgpack-cs.ll
amdpal-msgpack-es.ll
amdpal-msgpack-gs.ll
amdpal-msgpack-hs.ll
amdpal-msgpack-ls.ll
amdpal-msgpack-ps.ll
amdpal-msgpack-psenable.ll
amdpal-msgpack-vs.ll
amdpal-ps.ll
amdpal-psenable.ll
amdpal-vs.ll
amdpal.ll
and_or.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
and-gcn.ll
and.ll
andorbitset.ll
andorn2.ll
andorxorinvimm.ll
annotate-kernel-features-hsa-call.ll
annotate-kernel-features-hsa.ll
annotate-kernel-features.ll
anonymous-gv.ll
any_extend_vector_inreg.ll
anyext.ll
are-loads-from-same-base-ptr.ll
array-ptr-calc-i32.ll
array-ptr-calc-i64.ll
ashr.v2i16.ll
atomic_cmp_swap_local.ll
atomic_load_add.ll
atomic_load_local.ll
atomic_load_sub.ll
atomic_optimizations_buffer.ll
[AMDGPU] Simplify the exclusive scan used for optimized atomics
2019-07-19 08:40:37 +00:00
atomic_optimizations_global_pointer.ll
[AMDGPU] Fix DPP combiner check for exec modification
2019-07-12 15:59:40 +00:00
atomic_optimizations_local_pointer.ll
[AMDGPU] Optimize atomic AND/OR/XOR
2019-07-17 13:40:03 +00:00
atomic_optimizations_pixelshader.ll
[AMDGPU] Fix DPP combiner check for exec modification
2019-07-12 15:59:40 +00:00
atomic_optimizations_raw_buffer.ll
[AMDGPU] Fix DPP combiner check for exec modification
2019-07-12 15:59:40 +00:00
atomic_optimizations_struct_buffer.ll
[AMDGPU] Fix DPP combiner check for exec modification
2019-07-12 15:59:40 +00:00
atomic_store_local.ll
atomicrmw-nand.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
attr-amdgpu-flat-work-group-size-v3.ll
attr-amdgpu-flat-work-group-size.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
attr-amdgpu-num-sgpr-spill-to-smem.ll
attr-amdgpu-num-sgpr.ll
attr-amdgpu-num-vgpr.ll
attr-amdgpu-waves-per-eu.ll
attr-unparseable.ll
barrier-elimination.ll
basic-branch.ll
[AMDGPU] more gfx1010 tests. NFC.
2019-06-12 18:44:11 +00:00
basic-call-return.ll
basic-loop.ll
bfe_uint.ll
bfe-combine.ll
bfe-patterns.ll
bfi_int.ll
bfm.ll
big_alu.ll
bitcast-constant-to-vector.ll
bitcast-v4f16-v4i16.ll
bitcast-vector-extract.ll
bitreverse-inline-immediates.ll
bitreverse.ll
[DAG] Add SimplifyDemandedBits support for BITREVERSE
2019-05-11 20:56:05 +00:00
br_cc.f16.ll
branch-condition-and.ll
branch-relax-bundle.ll
branch-relax-spill.ll
AMDGPU: Reduce number of registers in test
2019-08-14 19:09:48 +00:00
branch-relaxation-debug-info.ll
branch-relaxation-inst-size-gfx10.ll
MC: Allow getMaxInstLength to depend on the subtarget
2019-05-22 16:28:41 +00:00
branch-relaxation.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
branch-uniformity.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
break-smem-soft-clauses.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
break-vmem-soft-clauses.mir
AMDGPU: Assume xnack is enabled by default
2019-05-16 14:48:34 +00:00
bswap.ll
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
buffer-schedule.ll
bug-vopc-commute.ll
build_vector.ll
build-vector-insert-elt-infloop.ll
build-vector-packed-partial-undef.ll
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
byval-frame-setup.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
call_fs.ll
call-argument-types.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
call-constexpr.ll
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00
call-encoding.ll
call-graph-register-usage.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
call-preserved-registers.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
call-return-types.ll
call-skip.ll
AMDGPU: Force skip branches over calls
2019-05-20 22:04:42 +00:00
call-to-kernel-undefined.ll
call-to-kernel.ll
call-waitcnt.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
callee-frame-setup.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
callee-special-input-sgprs.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
callee-special-input-vgprs.ll
[AMDGPU] Test update. NFC.
2019-07-22 18:08:53 +00:00
calling-conventions.ll
AMDGPU: Don't assert on v4f16 arguments to shader calling conventions
2019-07-25 13:55:07 +00:00
captured-frame-index.ll
cayman-loop-bug.ll
cf_end.ll
cf-loop-on-constant.ll
cf-stack-bug.ll
cgp-addressing-modes-flat.ll
cgp-addressing-modes.ll
cgp-bitfield-extract.ll
chain-hi-to-lo.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
clamp-modifier.ll
clamp-omod-special-case.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
clamp.ll
cluster-flat-loads-postra.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
cluster-flat-loads.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
cndmask-no-def-vcc.ll
coalescer_distribute.ll
coalescer_remat.ll
coalescer-extend-pruned-subrange.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
coalescer-identical-values-undef.mir
coalescer-subranges-another-copymi-not-live.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
coalescer-subranges-another-prune-error.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
coalescer-subranges-prune-kill-copy.mir
Fix register coalescer failure to prune value
2019-05-21 19:32:41 +00:00
coalescer-subreg-join.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
coalescer-subregjoin-fullcopy.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
coalescer-with-subregs-bad-identical.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
coalescing-with-subregs-in-loop-bug.mir
code-object-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
codegen-prepare-addrmode-sext.ll
collapse-endcf2.mir
AMDGPU: Assume calls read exec
2019-05-21 23:23:16 +00:00
collapse-endcf-broken.mir
collapse-endcf.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
collapse-endcf.mir
Reapply "AMDGPU: Split block for si_end_cf"
2019-08-01 01:25:27 +00:00
combine_vloads.ll
combine-and-sext-bool.ll
combine-cond-add-sub.ll
combine-ftrunc.ll
comdat.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
commute_modifiers.ll
commute-compares.ll
commute-shifts.ll
[Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
2019-07-24 22:57:22 +00:00
complex-folding.ll
computeKnownBits-scalar-to-vector-crash.ll
concat_vectors.ll
constant-address-space-32bit.ll
AMDGPU: Fix folding immediate into readfirstlane through reg_sequence
2019-06-19 20:44:15 +00:00
constant-fold-imm-immreg.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
constant-fold-mi-operands.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
control-flow-fastregalloc.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
control-flow-optnone.ll
[StructurizeCFG] Enable -structurizecfg-relaxed-uniform-regions by default
2019-08-06 14:30:19 +00:00
convergent-inlineasm.ll
copy-illegal-type.ll
copy-to-reg.ll
couldnt-join-subrange-3.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
cross-block-use-is-not-abi-copy.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
csr-gfx10.ll
AMDGPU: Fix not marking new gfx10 SGPRs as CSRs
2019-05-21 23:23:05 +00:00
ctlz_zero_undef.ll
ctlz.ll
[AMDGPU] Regenerate CTLZ tests for an upcoming patch
2019-05-31 15:06:14 +00:00
ctpop16.ll
ctpop64.ll
ctpop.ll
cttz_zero_undef.ll
cube.ll
cvt_f32_ubyte.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
cvt_flr_i32_f32.ll
cvt_rpi_i32_f32.ll
dag-divergence.ll
dagcomb-shuffle-vecextend-non2.ll
dagcombine-reassociate-bug.ll
dagcombine-select.ll
dagcombine-setcc-select.ll
dagcombiner-bug-illegal-vec4-int-to-fp.ll
dce-disjoint-intervals.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
dead_copy.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
dead-lane.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
dead-mi-use-same-intr.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
debug-value2.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
debug-value-scheduler-crash.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
debug-value.ll
debug.ll
[AMDGPU] Fix +DumpCode to print an entry label for the first function
2019-06-27 08:19:28 +00:00
default-fp-mode.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
detect-dead-lanes.mir
directive-amdgcn-target.ll
disable_form_clauses.ll
[AMDGPU] Added target-specific attribute amdgpu-max-memory-clause
2019-05-30 18:46:34 +00:00
disconnected-predset-break-bug.ll
div_i128.ll
[Testing] Fix tests that break with read-only checkouts
2019-08-01 06:41:40 +00:00
diverge-extra-formal-args.ll
diverge-interp-mov-lower.ll
diverge-switch-default.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
divergence-at-use.ll
[AMDGPU] Add amdgpu_kernel for consistency with other tests
2019-07-29 11:48:17 +00:00
divergent-branch-uniform-condition.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
divrem24-assume.ll
dpp_combine.mir
[AMDGPU] Fix DPP combiner check for exec modification
2019-07-12 15:59:40 +00:00
drop-mem-operand-move-smrd.ll
ds_read2_offset_order.ll
ds_read2_superreg.ll
ds_read2.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
ds_read2st64.ll
ds_write2.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
ds_write2st64.ll
ds-combine-large-stride.ll
ds-combine-with-dependence.ll
ds-negative-offset-addressing-mode-loop.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
ds-sub-offset.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
dynamic_stackalloc.ll
early-if-convert-cost.ll
early-if-convert.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
early-inline-alias.ll
early-inline.ll
elf-header-flags-mach.ll
[AMDGPU] gfx908 target
2019-07-09 18:10:06 +00:00
elf-header-flags-sram-ecc.ll
[AMDGPU] gfx908 target
2019-07-09 18:10:06 +00:00
elf-header-flags-xnack.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
elf-header-osabi.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
elf-notes.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
elf.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
elf.metadata.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
elf.r600.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
else.ll
empty-function.ll
enable-no-signed-zeros-fp-math.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
endcf-loop-header.ll
endpgm-dce.mir
AMDGPU: Add some tests for inlineasm behavior
2019-05-21 23:23:12 +00:00
enqueue-kernel.ll
exceed-max-sgprs.ll
extend-bit-ops-i16.ll
extload-align.ll
extload-private.ll
extload.ll
extract_subvector_vec4_vec3.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
extract_vector_dynelt.ll
extract_vector_elt-f16.ll
extract_vector_elt-f64.ll
extract_vector_elt-i8.ll
extract_vector_elt-i16.ll
extract_vector_elt-i64.ll
extract-lowbits.ll
extract-subvector-equal-length.ll
extract-vector-elt-build-vector-combine.ll
extractelt-to-trunc.ll
fabs.f16.ll
fabs.f64.ll
fabs.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
fadd64.ll
fadd-fma-fmul-combine.ll
fadd.f16.ll
fadd.ll
fcanonicalize-elimination.ll
fcanonicalize.f16.ll
fcanonicalize.ll
[AMDGPU] gfx1010 tests. NFC.
2019-05-13 19:30:06 +00:00
fceil64.ll
fceil.ll
fcmp64.ll
fcmp-cnd.ll
fcmp-cnde-int-args.ll
fcmp.f16.ll
fcmp.ll
fconst64.ll
fcopysign.f16.ll
fcopysign.f32.ll
fcopysign.f64.ll
fdiv32-to-rcp-folding.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
fdiv.f16.ll
[AMDGPU] gfx1010: use fmac instructions
2019-05-04 04:20:37 +00:00
fdiv.f64.ll
fdiv.ll
Re-commit: [AMDGPU] Use S_DENORM_MODE for gfx10
2019-08-06 02:16:11 +00:00
fdot2.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
fence-barrier.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
fetch-limits.r600.ll
fetch-limits.r700+.ll
fexp.ll
ffloor.f64.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
ffloor.ll
fix-sgpr-copies.mir
[AMDGPU] Fix the mis-handling of vreg_1 copied from scalar register.
2019-05-28 16:29:39 +00:00
fix-vgpr-copies.mir
fix-wwm-vgpr-copy.ll
flat_atomics_i64.ll
flat_atomics.ll
flat-address-space.ll
flat-error-unsupported-gpu-hsa.ll
flat-for-global-subtarget-feature.ll
flat-load-clustering.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
flat-offset-bug.ll
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
flat-scratch-reg.ll
floor.ll
fma-combine.ll
fma.f64.ll
fma.ll
fmac.sdwa.ll
[AMDGPU] Enable v4f16 and above for v_pk_fma instructions
2019-07-29 08:15:10 +00:00
fmad.ll
fmax3.f64.ll
fmax3.ll
fmax_legacy.f16.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fmax_legacy.f64.ll
fmax_legacy.ll
fmax.ll
fmaxnum.f64.ll
fmaxnum.ll
fmaxnum.r600.ll
fmed3.ll
fmin3.ll
fmin_fmax_legacy.amdgcn.ll
fmin_legacy.f16.ll
[DAGCombine] narrowInsertExtractVectorBinOp - add CONCAT_VECTORS support
2019-07-11 14:45:03 +00:00
fmin_legacy.f64.ll
fmin_legacy.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
fmin.ll
fminnum.f64.ll
fminnum.ll
fminnum.r600.ll
fmul64.ll
fmul-2-combine-multi-use.ll
[AMDGPU] more gfx1010 tests. NFC.
2019-06-12 18:44:11 +00:00
fmul.f16.ll
fmul.ll
fmuladd.f16.ll
[AMDGPU] gfx1010: use fmac instructions
2019-05-04 04:20:37 +00:00
fmuladd.f32.ll
fmuladd.f64.ll
fmuladd.v2f16.ll
fnearbyint.ll
fneg-combines.ll
Migrate some more fadd and fsub cases away from UnsafeFPMath control to utilize NoSignedZerosFPMath options control
2019-07-31 21:57:28 +00:00
fneg-combines.si.ll
fneg-fabs.f16.ll
[DAGCombine] GetNegatedExpression - constant float vector support (PR42105)
2019-06-11 09:44:33 +00:00
fneg-fabs.f64.ll
fneg-fabs.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
fneg.f16.ll
fneg.f64.ll
fneg.ll
fold-cndmask.mir
fold-fi-mubuf.mir
AMDGPU: Fold frame index into MUBUF
2019-06-24 14:53:56 +00:00
fold-fi-operand-shrink.mir
AMDGPU: Support shrinking add with FI in SIFoldOperands
2019-05-03 15:21:53 +00:00
fold-fmul-to-neg-abs.ll
fold-imm-copy.mir
AMDGPU: Fix test verification
2019-05-03 13:42:55 +00:00
fold-imm-f16-f32.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
fold-immediate-operand-shrink-with-carry.mir
fold-immediate-operand-shrink.mir
AMDGPU: Replace shrunk instruction with dummy implicit_def
2019-05-03 14:40:10 +00:00
fold-immediate-output-mods.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
fold-implicit-operand.mir
fold-multiple.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
fold-operands-order.mir
fold-readlane.mir
[AMDGPU] Fix to 'Fold readlane from copy of SGPR or imm'
2019-08-13 18:57:55 +00:00
fold-vgpr-copy.mir
force-alwaysinline-lds-global-address-codegen.ll
force-alwaysinline-lds-global-address.ll
fp16_to_fp32.ll
fp16_to_fp64.ll
fp32_to_fp16.ll
fp_to_sint.f64.ll
fp_to_sint.ll
fp_to_uint.f64.ll
fp_to_uint.ll
fp-atomic-to-s_denormmode.mir
[AMDGPU] hazard recognizer for fp atomic to s_denorm_mode
2019-06-21 16:30:14 +00:00
fp-classify.ll
fpext-free.ll
fpext.f16.ll
fpext.ll
fptosi.f16.ll
fptoui.f16.ll
fptrunc.f16.ll
fptrunc.ll
fract.f64.ll
fract.ll
frame-index-elimination.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
frame-lowering-entry-all-sgpr-used.mir
[AMDGPU] Skip calculating callee saved registers for entry function.
2019-07-11 23:53:30 +00:00
frame-lowering-fp-adjusted.mir
[AMDGPU] Add the adjusted FP as a livein register.
2019-07-16 15:57:12 +00:00
frem.ll
fsqrt.f64.ll
fsqrt.ll
fsub64.ll
fsub.f16.ll
fsub.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
ftrunc.f64.ll
ftrunc.ll
function-args.ll
AMDGPU: Don't fix emergency stack slot at offset 0
2019-06-05 22:37:50 +00:00
function-call-relocs.ll
function-returns.ll
AMDGPU: Add some function return test cases
2019-07-19 16:45:48 +00:00
gds-atomic.ll
AMDGPU: Support GDS atomics
2019-07-01 17:17:45 +00:00
gep-address-space.ll
gfx10-vop-literal.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
gfx902-without-xnack.ll
global_atomics_i64.ll
global_atomics.ll
global_smrd_cfg.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
global_smrd.ll
global-constant.ll
global-directive.ll
global-extload-i16.ll
global-load-store-atomics.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
global-saddr.ll
global-smrd-unknown.ll
global-variable-relocs.ll
gv-const-addrspace.ll
gv-offset-folding.ll
gws-hazards.mir
Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics"
2019-06-19 19:55:27 +00:00
half.ll
hazard-buffer-store-v-interp.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
hazard-hidden-bundle.mir
[AMDGPU] Enable serializing of argument info.
2019-07-03 02:00:21 +00:00
hazard-in-bundle.mir
[AMDGPU] gfx1010: small test change for wave32. NFC
2019-06-13 19:05:04 +00:00
hazard-inlineasm.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
hazard-kill.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
hazard.mir
hoist-cond.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
hsa-default-device.ll
hsa-fp-mode.ll
hsa-func-align.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-func.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-globals.ll
hsa-group-segment.ll
hsa-metadata-deduce-ro-arg-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-deduce-ro-arg.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-enqueue-kernel-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-enqueue-kernel.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-from-llvm-ir-full-v3.ll
[AMDGPU] Added a new metadata for multi grid sync implicit argument
2019-07-05 16:05:17 +00:00
hsa-metadata-from-llvm-ir-full.ll
[AMDGPU] Added a new metadata for multi grid sync implicit argument
2019-07-05 16:05:17 +00:00
hsa-metadata-hidden-args-v3.ll
[AMDGPU] Added a new metadata for multi grid sync implicit argument
2019-07-05 16:05:17 +00:00
hsa-metadata-hidden-args.ll
[AMDGPU] Added a new metadata for multi grid sync implicit argument
2019-07-05 16:05:17 +00:00
hsa-metadata-images-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-images.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-1-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-1.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-2-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-2.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-3-v3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-invalid-ocl-version-3.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-kernel-code-props-v3.ll
[AMDGPU] Fix high occupancy calculation and print it
2019-07-31 01:07:10 +00:00
hsa-metadata-kernel-code-props.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
hsa-metadata-wavefrontsize.ll
[AMDGPU] gfx1010 wave32 metadata
2019-06-17 16:48:56 +00:00
hsa-note-no-func.ll
[AMDGPU] gfx908 target
2019-07-09 18:10:06 +00:00
hsa.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
huge-private-buffer.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
i1-copies-rpo.mir
AMDGPU: Make fixing i1 copies robust against re-ordering
2019-06-27 16:56:44 +00:00
i1-copy-from-loop.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
i1-copy-implicit-def.ll
i1-copy-phi-uniform-branch.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
i1-copy-phi.ll
[SelectionDAG] Enhance the simplification of copyto from implicit-def.
2019-05-27 18:26:29 +00:00
i8-to-double-to-float.ll
icmp64.ll
icmp-select-sete-reverse-args.ll
icmp.i16.ll
idiv-licm.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
idot2.ll
[AMDGPU] Regenerate idot tests. NFCI.
2019-07-11 10:37:58 +00:00
idot4s.ll
[TargetLowering] Add SimplifyMultipleUseDemandedBits
2019-07-23 12:39:08 +00:00
idot4u.ll
[TargetLowering] Add SimplifyMultipleUseDemandedBits
2019-07-23 12:39:08 +00:00
idot8s.ll
[SelectionDAG] Check for any recursion depth greater than or equal to limit instead of just equal the limit.
2019-07-27 12:48:46 +00:00
idot8u.ll
[SelectionDAG] Check for any recursion depth greater than or equal to limit instead of just equal the limit.
2019-07-27 12:48:46 +00:00
illegal-sgpr-to-vgpr-copy.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
image_ls_mipmap_zero.ll
[AMDGPU] Optimize image_[load|store]_mip
2019-06-10 15:58:51 +00:00
image-attributes.ll
image-resource-id.ll
image-schedule.ll
img-nouse-adjust.ll
imm16.ll
imm.ll
immv216.ll
implicit-def-muse.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
indirect-addressing-si-gfx9.ll
indirect-addressing-si-noopt.ll
indirect-addressing-si-pregfx9.ll
indirect-addressing-si.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
indirect-addressing-term.ll
RegAllocFast: Improve hinting heuristic
2019-05-16 12:50:39 +00:00
indirect-private-64.ll
infer-addrpace-pipeline.ll
infinite-loop-evergreen.ll
infinite-loop.ll
inline-asm.ll
[AMDGPU] Correct the handling of inlineasm output registers.
2019-05-28 19:37:09 +00:00
inline-attr.ll
Add, and infer, a nofree function attribute
2019-07-08 15:57:56 +00:00
inline-calls.ll
inline-constraints.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
inline-maxbb.ll
[AMDGPU] Don't constrain callees with inlinehint from inlining on MaxBB check
2019-06-14 16:37:33 +00:00
inlineasm-16.ll
inlineasm-illegal-type.ll
inlineasm-packed.ll
InlineAsmCrash.ll
input-mods.ll
insert_subreg.ll
insert_vector_dynelt.ll
insert_vector_elt.ll
[AMDGPU] Regenerate tests.
2019-07-27 14:32:23 +00:00
insert_vector_elt.v2i16.ll
[AMDGPU] Regenerate v2i16 insertelement tests.
2019-07-29 09:47:07 +00:00
insert_vector_elt.v2i16.subtest-nosaddr.ll
insert_vector_elt.v2i16.subtest-saddr.ll
insert-skip-from-vcc.mir
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
insert-skips-flat-vmem.mir
AMDGPU: Fix MIR test verifier error
2019-06-07 17:55:07 +00:00
insert-skips-gws.mir
Reapply "AMDGPU: Add ds_gws_init / ds_gws_barrier intrinsics"
2019-06-19 19:55:27 +00:00
insert-skips-ignored-insts.mir
AMDGPU: Don't count mask branch pseudo towards skip threshold
2019-06-07 00:14:55 +00:00
insert-skips-kill-uncond.mir
insert-subvector-unused-scratch.ll
[AMDGPU] Custom lower INSERT_SUBVECTOR v3, v4, v5, v8
2019-07-04 17:38:24 +00:00
insert-waitcnts-callee.mir
insert-waitcnts-exp.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
inserted-wait-states.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
internalize.ll
invalid-addrspacecast.ll
invalid-alloca.ll
invariant-load-no-alias-store.ll
invert-br-undef-vcc.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
ipra-regmask.ll
[AMDGPU] gfx908 register file changes
2019-07-09 19:41:51 +00:00
ipra.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
jump-address.ll
kcache-fold.ll
kernarg-stack-alignment.ll
kernel-args.ll
kernel-argument-dag-lowering.ll
known-never-nan.ll
known-never-snan.ll
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
knownbits-recursion.ll
large-alloca-compute.ll
[AMDGPU] gfx1010 tests. NFC.
2019-05-13 19:30:06 +00:00
large-alloca-graphics.ll
large-constant-initializer.ll
large-work-group-promote-alloca.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
lcssa-optnone.ll
[AMDGPU] Run unreachable-mbb-elimination after isel to clean up PHIs.
2019-07-25 14:50:18 +00:00
lds_atomic_f32.ll
lds-alignment.ll
lds-bounds.ll
lds-branch-vmem-hazard.mir
AMDGPU] gfx1010 hazard recognizer
2019-05-04 04:30:57 +00:00
lds-global-non-entry-func.ll
lds-initializer.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
lds-m0-init-in-loop.ll
lds-misaligned-bug.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
lds-oqap-crash.ll
lds-output-queue.ll
lds-relocs.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
lds-size.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
lds-zero-initializer.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
legalize-fp-load-invariant.ll
legalizedag-bug-expand-setcc.ll
limit-coalesce.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
lit.local.cfg
literals.ll
liveness.mir
llvm.amdgcn.alignb.ll
llvm.amdgcn.atomic.dec.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
llvm.amdgcn.atomic.fadd.ll
[AMDGPU] gfx908 atomic fadd and atomic pk_fadd
2019-07-11 00:10:17 +00:00
llvm.amdgcn.atomic.inc.ll
[SelectionDAG] Propagate alias metadata to target intrinsic nodes
2019-07-03 14:33:29 +00:00
llvm.amdgcn.buffer.atomic.ll
llvm.amdgcn.buffer.load.dwordx3.ll
llvm.amdgcn.buffer.load.format.d16.ll
llvm.amdgcn.buffer.load.format.ll
llvm.amdgcn.buffer.load.ll
AMDGPU: Fold frame index into MUBUF
2019-06-24 14:53:56 +00:00
llvm.amdgcn.buffer.store.dwordx3.ll
llvm.amdgcn.buffer.store.format.d16.ll
llvm.amdgcn.buffer.store.format.ll
llvm.amdgcn.buffer.store.ll
llvm.amdgcn.buffer.wbinvl1.ll
llvm.amdgcn.buffer.wbinvl1.sc.ll
llvm.amdgcn.buffer.wbinvl1.vol.ll
llvm.amdgcn.class.f16.ll
llvm.amdgcn.class.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
llvm.amdgcn.cos.f16.ll
llvm.amdgcn.cos.ll
llvm.amdgcn.cubeid.ll
llvm.amdgcn.cubema.ll
llvm.amdgcn.cubesc.ll
llvm.amdgcn.cubetc.ll
llvm.amdgcn.cvt.pk.i16.ll
llvm.amdgcn.cvt.pk.u16.ll
llvm.amdgcn.cvt.pknorm.i16.ll
llvm.amdgcn.cvt.pknorm.u16.ll
llvm.amdgcn.cvt.pkrtz.ll
[AMDGPU] Regenerate test file for upcoming patch. NFCI.
2019-07-19 15:43:56 +00:00
llvm.amdgcn.dispatch.id.ll
llvm.amdgcn.dispatch.ptr.ll
llvm.amdgcn.div.fixup.f16.ll
llvm.amdgcn.div.fixup.ll
llvm.amdgcn.div.fmas.ll
llvm.amdgcn.div.scale.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
llvm.amdgcn.ds.append.ll
AMDGPU: Fix dropping memref for ds append/consume
2019-06-14 21:01:24 +00:00
llvm.amdgcn.ds.bpermute.ll
llvm.amdgcn.ds.consume.ll
AMDGPU: Fix dropping memref for ds append/consume
2019-06-14 21:01:24 +00:00
llvm.amdgcn.ds.gws.barrier.ll
AMDGPU: Remove v0 workaround for DS_GWS_* instructions
2019-08-01 18:41:32 +00:00
llvm.amdgcn.ds.gws.init.ll
AMDGPU: Remove v0 workaround for DS_GWS_* instructions
2019-08-01 18:41:32 +00:00
llvm.amdgcn.ds.gws.sema.br.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.p.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.release.all.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.gws.sema.v.ll
AMDGPU: Don't rely on m0 being -1 for GWS offsets
2019-07-19 20:01:24 +00:00
llvm.amdgcn.ds.ordered.add.gfx10.ll
AMDGPU/GFX10: implement ds_ordered_count changes
2019-07-01 17:17:52 +00:00
llvm.amdgcn.ds.ordered.add.ll
llvm.amdgcn.ds.ordered.swap.ll
Reapply "AMDGPU: Split block for si_end_cf"
2019-08-01 01:25:27 +00:00
llvm.amdgcn.ds.permute.ll
llvm.amdgcn.ds.swizzle.ll
llvm.amdgcn.exp.compr.ll
llvm.amdgcn.exp.ll
llvm.amdgcn.exp.prim.ll
[AMDGPU] gfx1010 exp modifications
2019-05-08 21:23:37 +00:00
llvm.amdgcn.fcmp.ll
llvm.amdgcn.fdiv.fast.ll
llvm.amdgcn.fdot2.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.fmad.ftz.f16.ll
llvm.amdgcn.fmad.ftz.ll
llvm.amdgcn.fmed3.f16.ll
llvm.amdgcn.fmed3.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
llvm.amdgcn.fmul.legacy.ll
llvm.amdgcn.fract.f16.ll
llvm.amdgcn.fract.ll
llvm.amdgcn.frexp.exp.f16.ll
llvm.amdgcn.frexp.exp.ll
llvm.amdgcn.frexp.mant.f16.ll
llvm.amdgcn.frexp.mant.ll
llvm.amdgcn.groupstaticsize.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
llvm.amdgcn.icmp.ll
llvm.amdgcn.image.a16.dim.ll
llvm.amdgcn.image.atomic.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.d16.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.dim.ll
[AMDGPU] gfx1010 GCNNSAReassign pass
2019-05-01 16:40:49 +00:00
llvm.amdgcn.image.gather4.a16.dim.ll
llvm.amdgcn.image.gather4.d16.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.gather4.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.gather4.o.dim.ll
llvm.amdgcn.image.getlod.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.load.a16.d16.ll
llvm.amdgcn.image.load.a16.ll
llvm.amdgcn.image.nsa.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.a16.dim.ll
llvm.amdgcn.image.sample.d16.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.dim.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.image.sample.ltolz.ll
llvm.amdgcn.image.sample.o.dim.ll
llvm.amdgcn.image.store.a16.d16.ll
llvm.amdgcn.image.store.a16.ll
llvm.amdgcn.implicit.buffer.ptr.hsa.ll
llvm.amdgcn.implicit.buffer.ptr.ll
AMDGPU: Revert accidental change to test
2019-07-01 19:09:57 +00:00
llvm.amdgcn.implicitarg.ptr.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
llvm.amdgcn.init.exec.ll
llvm.amdgcn.interp.f16.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
llvm.amdgcn.interp.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
llvm.amdgcn.kernarg.segment.ptr.ll
llvm.amdgcn.kill.ll
[AMDGPU] more gfx1010 tests. NFC.
2019-06-12 18:44:11 +00:00
llvm.amdgcn.ldexp.f16.ll
llvm.amdgcn.ldexp.ll
llvm.amdgcn.lerp.ll
llvm.amdgcn.log.clamp.ll
llvm.amdgcn.mbcnt.ll
llvm.amdgcn.mfma.ll
[AMDGPU] use v32f32 for 3 mfma intrinsics
2019-07-12 22:42:01 +00:00
llvm.amdgcn.mov.dpp8.ll
[AMDGPU] gfx1010 dpp16 and dpp8
2019-06-12 18:02:41 +00:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] gfx1010 dpp16 and dpp8
2019-06-12 18:02:41 +00:00
llvm.amdgcn.mqsad.pk.u16.u8.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
llvm.amdgcn.mqsad.u32.u8.ll
llvm.amdgcn.msad.u8.ll
llvm.amdgcn.mul.i24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
llvm.amdgcn.mul.u24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
llvm.amdgcn.permlane.ll
[AMDGPU] gfx1010 premlane instructions
2019-06-12 17:52:51 +00:00
llvm.amdgcn.ps.live.ll
llvm.amdgcn.qsad.pk.u16.u8.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
llvm.amdgcn.queue.ptr.ll
llvm.amdgcn.raw.buffer.atomic.ll
AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}
2019-08-05 09:36:06 +00:00
llvm.amdgcn.raw.buffer.load.format.d16.ll
llvm.amdgcn.raw.buffer.load.format.ll
llvm.amdgcn.raw.buffer.load.ll
AMDGPU: Correct behavior of f16 buffer loads
2019-08-05 15:59:07 +00:00
llvm.amdgcn.raw.buffer.store.format.d16.ll
llvm.amdgcn.raw.buffer.store.format.ll
llvm.amdgcn.raw.buffer.store.ll
AMDGPU: Correct behavior of f16/i16 non-format store intrinsics
2019-08-05 14:57:59 +00:00
llvm.amdgcn.raw.tbuffer.load.d16.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] gfx1010 tests. NFC.
2019-05-08 23:31:32 +00:00
llvm.amdgcn.raw.tbuffer.store.d16.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.raw.tbuffer.store.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.rcp.f16.ll
llvm.amdgcn.rcp.legacy.ll
llvm.amdgcn.rcp.ll
llvm.amdgcn.readfirstlane.ll
AMDGPU: Fold frame index into MUBUF
2019-06-24 14:53:56 +00:00
llvm.amdgcn.readlane.ll
AMDGPU: Fold readlane from copy of SGPR or imm
2019-06-18 12:23:46 +00:00
llvm.amdgcn.rsq.clamp.ll
llvm.amdgcn.rsq.f16.ll
llvm.amdgcn.rsq.legacy.ll
llvm.amdgcn.rsq.ll
llvm.amdgcn.s.barrier.ll
[DAGCombine][X86][AArch64][AMDGPU] (x - y) + -1 -> add (xor y, -1), x fold. Try 3
2019-05-30 20:37:29 +00:00
llvm.amdgcn.s.buffer.load.ll
llvm.amdgcn.s.dcache.inv.ll
llvm.amdgcn.s.dcache.inv.vol.ll
llvm.amdgcn.s.dcache.wb.ll
llvm.amdgcn.s.dcache.wb.vol.ll
llvm.amdgcn.s.decperflevel.ll
llvm.amdgcn.s.get.waveid.in.workgroup.ll
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
llvm.amdgcn.s.getpc.ll
llvm.amdgcn.s.getreg.ll
llvm.amdgcn.s.incperflevel.ll
llvm.amdgcn.s.memrealtime.ll
llvm.amdgcn.s.memtime.ll
llvm.amdgcn.s.sleep.ll
llvm.amdgcn.s.waitcnt.ll
AMDGPU: s_waitcnt field should be treated as unsigned
2019-07-11 23:42:57 +00:00
llvm.amdgcn.sad.hi.u8.ll
llvm.amdgcn.sad.u8.ll
llvm.amdgcn.sad.u16.ll
llvm.amdgcn.sbfe.ll
llvm.amdgcn.sdot2.ll
[AMDGPU] gfx908 dot instruction support
2019-07-11 00:00:27 +00:00
llvm.amdgcn.sdot4.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.sdot8.ll
[AMDGPU] gfx908 dot instruction support
2019-07-11 00:00:27 +00:00
llvm.amdgcn.sendmsg.ll
[AMDGPU][MC] Enabled constant expressions as operands of sendmsg
2019-06-28 14:14:02 +00:00
llvm.amdgcn.set.inactive.ll
llvm.amdgcn.sffbh.ll
llvm.amdgcn.sin.f16.ll
llvm.amdgcn.sin.ll
llvm.amdgcn.softwqm.ll
[AMDGPU] Add llvm.amdgcn.softwqm intrinsic
2019-07-26 09:54:12 +00:00
llvm.amdgcn.struct.buffer.atomic.ll
AMDGPU: add missing llvm.amdgcn.{raw,struct}.buffer.atomic.{inc,dec}
2019-08-05 09:36:06 +00:00
llvm.amdgcn.struct.buffer.load.format.d16.ll
llvm.amdgcn.struct.buffer.load.format.ll
llvm.amdgcn.struct.buffer.load.ll
AMDGPU: Correct behavior of f16 buffer loads
2019-08-05 15:59:07 +00:00
llvm.amdgcn.struct.buffer.store.format.d16.ll
llvm.amdgcn.struct.buffer.store.format.ll
llvm.amdgcn.struct.buffer.store.ll
AMDGPU: Correct behavior of f16/i16 non-format store intrinsics
2019-08-05 14:57:59 +00:00
llvm.amdgcn.struct.tbuffer.load.d16.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.store.d16.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.struct.tbuffer.store.ll
[AMDGPU] gfx1010 MIMG implementation
2019-05-01 16:32:58 +00:00
llvm.amdgcn.tbuffer.load.d16.ll
llvm.amdgcn.tbuffer.load.dwordx3.ll
llvm.amdgcn.tbuffer.load.ll
llvm.amdgcn.tbuffer.store.d16.ll
llvm.amdgcn.tbuffer.store.dwordx3.ll
llvm.amdgcn.tbuffer.store.ll
llvm.amdgcn.trig.preop.ll
llvm.amdgcn.ubfe.ll
UpdateTestChecks: fix AMDGPU handling
2019-05-18 13:00:03 +00:00
llvm.amdgcn.udot2.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot4.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.udot8.ll
[AMDGPU] gfx1011/gfx1012 targets
2019-06-14 00:33:31 +00:00
llvm.amdgcn.unreachable.ll
llvm.amdgcn.update.dpp.ll
[AMDGPU] gfx1010 dpp16 and dpp8
2019-06-12 18:02:41 +00:00
llvm.amdgcn.wave.barrier.ll
llvm.amdgcn.wavefrontsize.ll
[AMDGPU] gfx1010 wavefrontsize intrinsic folding
2019-06-17 17:57:50 +00:00
llvm.amdgcn.workgroup.id.ll
llvm.amdgcn.workitem.id.ll
llvm.amdgcn.wqm.vote.ll
llvm.amdgcn.writelane.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
llvm.ceil.f16.ll
llvm.cos.f16.ll
llvm.cos.ll
llvm.dbg.value.ll
llvm.exp2.f16.ll
llvm.exp2.ll
llvm.floor.f16.ll
llvm.fma.f16.ll
[AMDGPU] Enable v4f16 and above for v_pk_fma instructions
2019-07-29 08:15:10 +00:00
llvm.fmuladd.f16.ll
[AMDGPU] gfx1010: use fmac instructions
2019-05-04 04:20:37 +00:00
llvm.log2.f16.ll
llvm.log2.ll
llvm.log10.f16.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
llvm.log10.ll
llvm.log.f16.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
llvm.log.ll
llvm.maxnum.f16.ll
llvm.memcpy.ll
AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0
2019-06-16 17:32:01 +00:00
llvm.minnum.f16.ll
llvm.pow.ll
llvm.r600.cube.ll
llvm.r600.dot4.ll
llvm.r600.group.barrier.ll
llvm.r600.read.local.size.ll
llvm.r600.recipsqrt.clamped.ll
llvm.r600.recipsqrt.ieee.ll
llvm.r600.tex.ll
llvm.rint.f16.ll
llvm.rint.f64.ll
llvm.rint.ll
llvm.round.f64.ll
llvm.round.ll
llvm.sin.f16.ll
llvm.sin.ll
llvm.sqrt.f16.ll
llvm.trunc.f16.ll
load-constant-f32.ll
load-constant-f64.ll
load-constant-i1.ll
load-constant-i8.ll
load-constant-i16.ll
load-constant-i32.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
load-constant-i64.ll
load-global-f32.ll
load-global-f64.ll
load-global-i1.ll
load-global-i8.ll
load-global-i16.ll
load-global-i32.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
load-global-i64.ll
load-hi16.ll
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
load-input-fold.ll
load-lo16.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
load-local-f32-no-ds128.ll
load-local-f32.ll
load-local-f64.ll
load-local-i1.ll
load-local-i8.ll
load-local-i16.ll
load-local-i32.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
load-local-i64.ll
load-select-ptr.ll
load-weird-sizes.ll
local-64.ll
local-atomics64.ll
local-atomics-fp.ll
local-atomics.ll
local-memory.amdgcn.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
local-memory.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
local-memory.r600.ll
local-stack-slot-offset.ll
loop_break.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
loop_exit_with_xor.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
loop-address.ll
loop-idiom.ll
AMDGPU: Fix tests using the default alloca address space
2019-07-01 15:23:03 +00:00
lower-kernargs.ll
lower-mem-intrinsics.ll
lower-range-metadata-intrinsic-call.ll
lshl64-to-32.ll
lshr.v2i16.ll
macro-fusion-cluster-vcc-uses.mir
mad24-get-global-id.ll
mad_64_32.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
mad_int24.ll
mad_uint24.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
mad-combine.ll
mad-mix-hi.ll
mad-mix-lo.ll
mad-mix.ll
mad.u16.ll
[AMDGPU] gfx1010 lost VOP2 forms of some add/sub
2019-05-02 04:26:35 +00:00
madak-inline-constant.mir
madak.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
madmk.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
mai-hazards.mir
[AMDGPU] gfx908 hazard recognizer
2019-07-11 21:30:34 +00:00
mai-inline.ll
[AMDGPU] gfx908 mfma support
2019-07-11 21:19:33 +00:00
max3.ll
max-literals.ll
max-sgprs.ll
[AMDGPU] gfx1010 VOP2 changes
2019-04-26 16:37:51 +00:00
max.i16.ll
max.ll
med3-no-simplify.ll
mem-builtins.ll
memory_clause.ll
memory_clause.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
memory-legalizer-amdpal.ll
memory-legalizer-atomic-cmpxchg.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
memory-legalizer-atomic-fence.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
memory-legalizer-atomic-insert-end.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
memory-legalizer-atomic-rmw.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
memory-legalizer-invalid-addrspace.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
memory-legalizer-invalid-syncscope.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
memory-legalizer-load.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
memory-legalizer-local.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
memory-legalizer-mesa3d.ll
memory-legalizer-multiple-mem-operands-atomics.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-1.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
memory-legalizer-multiple-mem-operands-nontemporal-2.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
memory-legalizer-region.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
memory-legalizer-store-infinite-loop.ll
memory-legalizer-store.ll
[AMDGPU] gfx1010 memory legalizer
2019-05-06 21:57:02 +00:00
merge-load-store-physreg.mir
merge-load-store-vreg.mir
merge-load-store.mir
AMDGPU/LoadStoreOptimizer: Set the correct offset whem merging MMOs
2019-08-05 16:08:44 +00:00
merge-m0.mir
[AMDGPU] Enable merging m0 initializations.
2019-07-15 22:07:05 +00:00
merge-store-crash.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
merge-store-usedef.ll
merge-stores.ll
mesa3d.ll
AMDGPU: Fix not adding ImplicitBufferPtr as a live-in
2019-05-31 22:47:36 +00:00
mesa_regression.ll
min3.ll
min.ll
[AMDGPU] gfx1010 lost VOP2 forms of some add/sub
2019-05-02 04:26:35 +00:00
mir-print-dead-csr-fi.mir
MIR: Fix printer crashing on dead CSR frame indexes
2019-05-28 13:08:31 +00:00
misched-killflags.mir
missing-store.ll
mixed_wave32_wave64.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
mixed-wave32-wave64.ll
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
mode-register.mir
move-addr64-rsrc-dead-subreg-writes.ll
move-to-valu-atomicrmw.ll
move-to-valu-worklist.ll
movreld-bug.ll
movrels-bug.mir
mubuf-legalize-operands.ll
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
mubuf-legalize-operands.mir
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
mubuf-offset-private.ll
mubuf-shader-vgpr.ll
mubuf.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
mul_int24.ll
mul_uint24-amdgcn.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
mul_uint24-r600.ll
mul.i16.ll
AMDGPU: Add 24-bit mul intrinsics
2019-07-15 17:50:31 +00:00
mul.ll
AMDGPU: Temporary drop s_mul_hi_i/u32 patterns
2019-05-28 21:18:34 +00:00
multi-divergent-exit-region.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
multi-dword-vgpr-spill.ll
AMDGPU: Don't fix emergency stack slot at offset 0
2019-06-05 22:37:50 +00:00
multilevel-break.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
nand.ll
nested-calls.ll
[AMDGPU] Created a sub-register class for the return address operand in the return instruction.
2019-07-09 16:48:42 +00:00
nested-loop-conditions.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
no-hsa-graphics-shaders.ll
no-initializer-constant-addrspace.ll
AMDGPU: Be explicit about whether the high-word in SI_PC_ADD_REL_OFFSET is 0
2019-06-16 17:32:01 +00:00
no-remat-indirect-mov.mir
no-shrink-extloads.ll
noop-shader-O0.ll
nop-data.ll
[llvm-objdump] Tidy up AMDGCNPrettyPrinter
2019-06-18 06:35:18 +00:00
nor.ll
not-scalarize-volatile-load.ll
nsa-reassign.ll
[AMDGPU] Fix high occupancy calculation and print it
2019-07-31 01:07:10 +00:00
nsa-vmem-hazard.mir
AMDGPU] gfx1010 hazard recognizer
2019-05-04 04:30:57 +00:00
nullptr.ll
occupancy-levels.ll
[AMDGPU] Fix high occupancy calculation and print it
2019-07-31 01:07:10 +00:00
omod-nsz-flag.mir
AMDGPU: Serialize mode from MachineFunctionInfo
2019-07-10 16:09:26 +00:00
omod.ll
opencl-image-metadata.ll
opencl-printf.ll
[AMDGPU] Printf runtime binding pass
2019-08-12 17:12:29 +00:00
operand-folding.ll
operand-spacing.ll
opt-sgpr-to-vgpr-copy.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
optimize-exec-masking-pre-ra.mir
AMDGPU: Forgot to commit test file for r358890
2019-05-03 13:55:40 +00:00
optimize-if-exec-masking.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
optimize-negated-cond-exec-masking-wave32.mir
[AMDGPU] gfx10 tests. NFC.
2019-06-20 16:29:40 +00:00
optimize-negated-cond-exec-masking.mir
[AMDGPU] Fixed addReg() in SIOptimizeExecMaskingPreRA.cpp
2019-04-23 17:59:26 +00:00
optimize-negated-cond.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
or3.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
or.ll
pack.v2f16.ll
pack.v2i16.ll
packed-op-sel.ll
packetizer.ll
parallelandifcollapse.ll
parallelorifcollapse.ll
partial-sgpr-to-vgpr-spills.ll
partial-shift-shrink.ll
partially-dead-super-register-immediate.ll
peephole-opt-regseq-removal.mir
pei-reg-scavenger-position.mir
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
perfhint.ll
permute.ll
phi-elimination-assertion.mir
pk_max_f16_literal.ll
[AMDGPU] gfx1010 allows VOP3 to have a literal
2019-05-02 04:01:39 +00:00
post-ra-sched-kill-bundle-use-inst.mir
ScheduleDAG: Fix incorrectly killing registers in bundles
2019-07-05 15:32:28 +00:00
postra-norename.mir
power-sched-no-instr-sunit.mir
[AMDGPU] fixed scheduler crash in gfx908
2019-07-15 15:34:05 +00:00
predicate-dp4.ll
predicates.ll
preserve-hi16.ll
[AMDGPU] gfx1010 VOP3 and VOP3P implementation
2019-04-26 17:56:03 +00:00
print-mir-custom-pseudo.ll
private-access-no-objects.ll
private-element-size.ll
private-memory-atomics.ll
private-memory-r600.ll
promote-alloca-addrspacecast.ll
promote-alloca-array-aggregate.ll
promote-alloca-array-allocation.ll
promote-alloca-bitcast-function.ll
promote-alloca-calling-conv.ll
AMDGPU: Remove amdgpu-max-work-group-size attribute
2019-06-05 20:32:32 +00:00
promote-alloca-globals.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
promote-alloca-invariant-markers.ll
promote-alloca-lifetime.ll
AMDGPU: Fix iterator crash in AMDGPUPromoteAlloca
2019-06-18 12:23:44 +00:00
promote-alloca-mem-intrinsics.ll
promote-alloca-no-opts.ll
promote-alloca-padding-size-estimate.ll
promote-alloca-stored-pointer-value.ll
promote-alloca-to-lds-icmp.ll
promote-alloca-to-lds-phi.ll
promote-alloca-to-lds-select.ll
promote-alloca-unhandled-intrinsic.ll
promote-alloca-vector-to-vector.ll
promote-alloca-volatile.ll
promote-constOffset-to-imm.ll
promote-constOffset-to-imm.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
propagate-attributes-bitcast-function.ll
[AMDGPU] Propagate function attributes thru bitcasts
2019-06-17 20:42:48 +00:00
propagate-attributes-clone.ll
[AMDGPU] Pass to propagate ABI attributes from kernels to the functions
2019-06-17 17:47:28 +00:00
propagate-attributes-single-set.ll
[AMDGPU] Pass to propagate ABI attributes from kernels to the functions
2019-06-17 17:47:28 +00:00
pv-packing.ll
pv.ll
r600-constant-array-fixup.ll
[llvm-readobj] Change -long-option to --long-option in tests. NFC
2019-05-01 05:27:20 +00:00
r600-encoding.ll
r600-export-fix.ll
r600-infinite-loop-bug-while-reorganizing-vector.ll
r600-legalize-umax-bug.ll
r600.add.ll
AMDGPU: Select VOP3 form of add
2019-05-08 22:09:57 +00:00
r600.alu-limits.ll
r600.amdgpu-alias-analysis.ll
r600.bitcast.ll
r600.extract-lowbits.ll
r600.func-alignment.ll
r600.global_atomics.ll
r600.private-memory.ll
r600.sub.ll
AMDGPU: Select VOP3 form of sub
2019-05-03 15:37:07 +00:00
r600.work-item-intrinsics.ll
r600cfg.ll
rcp_iflag.ll
rcp-pattern.ll
read_register.ll
read-register-invalid-subtarget.ll
read-register-invalid-type-i32.ll
read-register-invalid-type-i64.ll
readcyclecounter.ll
[AMDGPU] Always use s_memtime for readcyclecounter
2019-07-09 03:10:18 +00:00
readlane_exec0.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
README
reassoc-scalar.ll
reduce-build-vec-ext-to-ext-build-vec.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
reduce-load-width-alignment.ll
reduce-saveexec.mir
reduce-store-width-alignment.ll
reduction.ll
reg-coalescer-sched-crash.ll
regbank-reassign.mir
[AMDGPU] Fixed occupancy calculation for gfx10
2019-07-19 21:29:51 +00:00
regcoal-subrange-join-seg.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
regcoal-subrange-join.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
regcoalesce-cannot-join-failures.mir
regcoalesce-dbg.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
regcoalesce-keep-valid-lanes-implicit-def-bug39602.mir
regcoalesce-prune.mir
regcoalescing-remove-partial-redundancy-assert.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
register-count-comments.ll
rename-disconnected-bug.ll
rename-independent-subregs-mac-operands.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
rename-independent-subregs.mir
reorder-stores.ll
reqd-work-group-size.ll
ret_jump.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
ret.ll
AMDGPU/GlobalISel: Handle most function return types
2019-07-26 02:36:05 +00:00
returnaddress.ll
AMDGPU: Return address lowering
2019-05-29 18:20:11 +00:00
rewrite-out-arguments-address-space.ll
IR: print value numbers for unnamed function arguments
2019-08-03 14:28:34 +00:00
rewrite-out-arguments.ll
IR: print value numbers for unnamed function arguments
2019-08-03 14:28:34 +00:00
rotl.i64.ll
rotl.ll
rotr.i64.ll
rotr.ll
rsq.ll
rv7x0_count3.ll
s_addk_i32.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
s_code_end.ll
[AMDGPU] Increase kernel padding
2019-07-24 19:40:13 +00:00
s_movk_i32.ll
s_mulk_i32.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
sad.ll
saddo.ll
[AMDGPU] Regenerated saddo.ll test file for D47927
2019-08-02 17:52:55 +00:00
salu-to-valu.ll
[DAGCombiner] [CodeGenPrepare] More comprehensive GEP splitting
2019-06-17 10:54:12 +00:00
sampler-resource-id.ll
scalar_to_vector_v2x16.ll
scalar_to_vector.ll
[AMDGPU] Regenerate tests.
2019-07-27 14:32:23 +00:00
scalar-branch-missing-and-exec.ll
scalar-store-cache-flush.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sched-assert-onlydbg-value-empty-region.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sched-crash-dbg-value.mir
AMDGPU: Correct properties for adjcallstack* pseudos
2019-07-01 22:01:05 +00:00
schedule-fs-loop-nested-if.ll
schedule-fs-loop-nested.ll
schedule-fs-loop.ll
schedule-global-loads.ll
schedule-if-2.ll
schedule-if.ll
schedule-ilp.ll
schedule-kernel-arg-loads.ll
schedule-regpressure-limit2.ll
schedule-regpressure-limit3.ll
schedule-regpressure-limit.ll
schedule-regpressure.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
schedule-vs-if-nested-loop-failure.ll
schedule-vs-if-nested-loop.ll
scheduler-handle-move-bundle.mir
LiveIntervals: Fix handleMove asserting on BUNDLE
2019-07-19 19:32:00 +00:00
scheduler-subrange-crash.ll
scratch-buffer.ll
scratch-simple.ll
AMDGPU/GFX10: fix scratch resource descriptor
2019-07-01 15:43:00 +00:00
sdiv.ll
[TargetLowering] Add SimplifyMultipleUseDemandedBits
2019-07-23 12:39:08 +00:00
sdivrem24.ll
sdivrem64.ll
sdwa-gfx9.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sdwa-op64-test.ll
sdwa-ops.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sdwa-peephole-instr-gfx10.mir
[AMDGPU] gfx1010: use fmac instructions
2019-05-04 04:20:37 +00:00
sdwa-peephole-instr.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sdwa-peephole.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
sdwa-preserve.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sdwa-scalar-ops.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
sdwa-vop2-64bit.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
select64.ll
select-fabs-fneg-extract-legacy.ll
select-fabs-fneg-extract.ll
[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
2019-07-10 14:53:47 +00:00
select-i1.ll
select-opt.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
select-undef.ll
select-vectors.ll
select.f16.ll
select.ll
selectcc-cnd.ll
selectcc-cnde-int.ll
selectcc-icmp-select-float.ll
selectcc-opt.ll
selectcc.ll
sendmsg-m0-hazard.mir
set-dx10.ll
setcc64.ll
setcc-equivalent.ll
setcc-fneg-constant.ll
setcc-limit-load-shrink.ll
setcc-opt.ll
setcc-sext.ll
setcc.ll
seto.ll
setuo.ll
sext-eliminate.ll
sext-in-reg-failure-r600.ll
sext-in-reg.ll
sgpr-control-flow.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
sgpr-copy-duplicate-operand.ll
sgpr-copy.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
sgpr-limit.ll
[AMDGPU] Increases available SGPR for Calling Convention
2019-05-15 14:43:55 +00:00
sgpr-spill-wrong-stack-id.mir
AMDGPU: Correct properties for adjcallstack* pseudos
2019-07-01 22:01:05 +00:00
sgprcopies.ll
shader-addr64-nonuniform.ll
shared-op-cycle.ll
shift-and-i64-ubfe.ll
shift-and-i128-ubfe.ll
shift-i64-opts.ll
shift-i128.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
shl_add_constant.ll
[DAG] Refactor DAGCombiner::ReassociateOps
2019-04-29 17:50:10 +00:00
shl_add_ptr.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
shl_add.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
shl_or.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
shl-add-to-add-shl.ll
shl.ll
shl.v2i16.ll
shrink-add-sub-constant.ll
AMDGPU: Treat undef as an inline immediate
2019-06-20 16:01:09 +00:00
shrink-carry.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
shrink-vop3-carry-out.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
si-annotate-cf-noloop.ll
si-annotate-cf-unreachable.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
si-annotate-cf.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
si-annotate-cfg-loop-assert.ll
si-annotatecfg-multiple-backedges.ll
[AMDGPU] gfx1010 wave32 icmp/fcmp intrinsic changes for wave32
2019-06-13 23:47:36 +00:00
si-fix-sgpr-copies.mir
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
si-instr-info-correct-implicit-operands.ll
Rename ExpandISelPseudo->FinalizeISel, delay register reservation
2019-06-19 00:25:39 +00:00
si-lower-control-flow-kill.ll
si-lower-control-flow-unreachable-block.ll
si-lower-control-flow.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
si-lower-i1-copies.mir
AMDGPU: Fix LCSSA phi lowering in SILowerI1Copies
2019-04-23 13:12:52 +00:00
si-lower-sgpr-spills.mir
[AMDGPU] Add test case on crashing of si-lower-sgpr-spills pass
2019-07-19 18:50:53 +00:00
si-scheduler.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
si-sgpr-spill.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
si-spill-cf.ll
si-spill-sgpr-stack.ll
si-triv-disjoint-mem-access.ll
si-vector-hang.ll
sibling-call.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
sign_extend.ll
simplify-libcalls.ll
simplifydemandedbits-recursion.ll
sint_to_fp.f64.ll
sint_to_fp.i64.ll
[AMDGPU] Allow abs/neg source modifiers on v_cndmask_b32
2019-07-10 14:53:47 +00:00
sint_to_fp.ll
sitofp.f16.ll
skip-branch-taildup-ret.mir
AMDGPU: Insert skip branches over return blocks
2019-06-06 22:51:51 +00:00
skip-branch-trap.ll
AMDGPU: Force skips around traps
2019-06-07 23:02:52 +00:00
skip-if-dead.ll
smed3.ll
smem-no-clause-coalesced.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
smem-war-hazard.mir
[AMDGPU] more gfx1010 tests. NFC.
2019-06-12 18:44:11 +00:00
sminmax.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
sminmax.v2i16.ll
AMDGPU: Undo sub x, c canonicalization for v2i16
2019-06-19 23:37:43 +00:00
smrd-fold-offset.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
smrd-gfx10.ll
AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsic
2019-06-16 17:14:12 +00:00
smrd-vccz-bug.ll
smrd.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
sopk-compares.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
sp-too-many-input-sgprs.ll
AMDGPU: Invert frame index offset interpretation
2019-06-05 22:20:47 +00:00
spill-agpr.ll
[AMDGPU] use v32f32 for 3 mfma intrinsics
2019-07-12 22:42:01 +00:00
spill-alloc-sgpr-init-bug.ll
spill-before-exec.mir
AMDGPU: Fix test failing since r365512
2019-07-09 17:54:34 +00:00
spill-cfg-position.ll
AMDGPU: Assume xnack is enabled by default
2019-05-16 14:48:34 +00:00
spill-csr-frame-ptr-reg-copy.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
spill-empty-live-interval.mir
AMDGPU: Invert frame index offset interpretation
2019-06-05 22:20:47 +00:00
spill-m0.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
spill-offset-calculation.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
spill-scavenge-offset.ll
spill-to-smem-m0.ll
spill-vgpr-to-agpr.ll
[AMDGPU] Reserve all AGPRs on targets which do not have them
2019-07-30 19:29:33 +00:00
spill-wide-sgpr.ll
split-arg-dbg-value.ll
AMDGPU: Attempt to fix bot error
2019-07-19 14:56:24 +00:00
split-scalar-i64-add.ll
split-smrd.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
split-vector-memoperand-offsets.ll
splitkit.mir
sra.ll
sram-ecc-default.ll
srem.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
srl.ll
ssubo.ll
stack-realign-kernel.ll
AMDGPU: Disable stack realignment for kernels
2019-06-03 21:33:22 +00:00
stack-realign.ll
AMDGPU: Make s34 the FP register
2019-07-08 19:03:38 +00:00
stack-size-overflow.ll
stack-slot-color-sgpr-vgpr-spills.mir
Describe stack-id as an enum
2019-06-17 09:13:29 +00:00
store_typed.ll
store-barrier.ll
store-global.ll
store-hi16.ll
AMDGPU: Always use s33 for global scratch wave offset
2019-06-20 21:58:24 +00:00
store-local.ll
store-private.ll
store-v3i64.ll
store-vector-ptrs.ll
store-weird-sizes.ll
[AMDGPU] Reapplied BFE canonicalization from D60462
2019-05-08 15:49:10 +00:00
stress-calls.ll
structurize1.ll
structurize.ll
sub_i1.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
sub.i16.ll
AMDGPU: Explicitly define a triple for some tests
2019-06-17 19:25:57 +00:00
sub.ll
AMDGPU: Select VOP3 form of sub
2019-05-03 15:37:07 +00:00
sub.v2i16.ll
[AMDGPU] Regenerate vector sub tests
2019-05-23 11:27:28 +00:00
subreg_interference.mir
subreg-coalescer-crash.ll
subreg-coalescer-undef-use.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
subreg-eliminate-dead.ll
subreg-intervals.mir
subreg-split-live-in-error.mir
AMDGPU: Invert frame index offset interpretation
2019-06-05 22:20:47 +00:00
subvector-test.mir
[AMDGPU] gfx1010 subvector test. NFC.
2019-06-17 21:55:06 +00:00
swizzle-export.ll
syncscopes.ll
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
tail-call-cgp.ll
tail-duplication-convergent.ll
AMDGPU: Add intrinsics for DS GWS semaphore instructions
2019-06-20 21:11:42 +00:00
target-cpu.ll
AMDGPU: Write LDS objects out as global symbols in code generation
2019-06-25 11:52:30 +00:00
tex-clause-antidep.ll
texture-input-merge.ll
trap.ll
trunc-bitcast-vector.ll
trunc-cmp-constant.ll
trunc-combine.ll
[AMDGPU] Regenerate tests.
2019-07-27 14:32:23 +00:00
trunc-store-f64-to-f16.ll
trunc-store-i1.ll
trunc-store.ll
trunc-vector-store-assertion-failure.ll
trunc.ll
tti-unroll-prefs.ll
twoaddr-fma.mir
[AMDGPU] gfx1010: use fmac instructions
2019-05-04 04:20:37 +00:00
twoaddr-mad.mir
uaddo.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
udiv.ll
udivrem24.ll
udivrem64.ll
udivrem.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
uint_to_fp.f64.ll
uint_to_fp.i64.ll
uint_to_fp.ll
uitofp.f16.ll
umed3.ll
unaligned-load-store.ll
undefined-physreg-sgpr-spill.mir
[AMDGPU] Correct the setting of FlatScratchInit.
2019-07-04 13:29:45 +00:00
undefined-subreg-liverange.ll
unhandled-loop-condition-assertion.ll
uniform-branch-intrinsic-cond.ll
uniform-cfg.ll
uniform-crash.ll
uniform-loop-inside-nonuniform.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
uniform-work-group-attribute-missing.ll
uniform-work-group-nested-function-calls.ll
uniform-work-group-prevent-attribute-propagation.ll
uniform-work-group-propagate-attribute.ll
uniform-work-group-recursion-test.ll
uniform-work-group-test.ll
unify-metadata.ll
unigine-liveness-crash.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
unknown-processor.ll
unpack-half.ll
unroll.ll
AMDGPU: Fix tests using the default alloca address space
2019-07-01 15:23:03 +00:00
unsupported-calls.ll
unsupported-cc.ll
update-phi.ll
Update phis in AMDGPUUnifyDivergentExitNodes
2019-06-25 18:55:16 +00:00
urem.ll
[AMDGPU] gfx1010: prefer V_MUL_LO_U32 over V_MUL_LO_I32
2019-05-06 22:27:05 +00:00
use-sgpr-multiple-times.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
usubo.ll
AMDGPU: Fix capitalized register names in asm constraints
2019-06-14 21:16:06 +00:00
v1i64-kernel-arg.ll
v1024.ll
[AMDGPU] Change register type for v32 vectors
2019-07-16 20:06:00 +00:00
v_cndmask.ll
[AMDGPU] Restrict v_cndmask_b32 abs/neg modifiers to f32
2019-07-12 15:02:59 +00:00
v_cvt_pk_u8_f32.ll
v_mac_f16.ll
v_mac.ll
v_madak_f16.ll
v_swap_b32.mir
valu-i1.ll
[MBP] Move a latch block with conditional exit and multi predecessors to top of loop
2019-06-14 23:08:59 +00:00
vccz-corrupt-bug-workaround.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
vcmpx-exec-war-hazard.mir
[AMDGPU] more gfx1010 tests. NFC.
2019-06-12 18:44:11 +00:00
vcmpx-permlane-hazard.mir
[AMDGPU] gfx1010 premlane instructions
2019-06-12 17:52:51 +00:00
vector_shuffle.packed.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
vector-alloca-addrspacecast.ll
vector-alloca-atomic.ll
vector-alloca.ll
vector-extract-insert.ll
vector-legalizer-divergence.ll
vectorize-buffer-fat-pointer.ll
vectorize-global-local.ll
verify-sop.mir
AMDGPU: Verify that SOP2/SOPC instructions have at most one immediate operand
2019-05-07 09:19:09 +00:00
vertex-fetch-encoding.ll
vgpr-spill-emergency-stack-slot-compute.ll
[AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fdd
2019-06-06 21:13:02 +00:00
vgpr-spill-emergency-stack-slot.ll
AMDGPU: Drop remnants of byval support for shaders
2019-07-12 20:12:17 +00:00
vi-removed-intrinsics.ll
virtregrewrite-undef-identity-copy.mir
AMDGPU: Correct properties for adjcallstack* pseudos
2019-07-01 22:01:05 +00:00
vmem-to-salu-hazard.mir
AMDGPU/GFX10: Apply the VMEM-to-scalar-write hazard also to writes to EXEC
2019-07-17 11:22:57 +00:00
vmem-vcc-hazard.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
vop-shrink-frame-index.mir
vop-shrink-non-ssa.mir
vop-shrink.ll
vselect64.ll
vselect.ll
vtx-fetch-branch.ll
vtx-schedule.ll
wait.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
waitcnt-back-edge-loop.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
waitcnt-debug.mir
waitcnt-flat.ll
waitcnt-loop-irreducible.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
waitcnt-loop-single-basic-block.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
waitcnt-looptest.ll
waitcnt-no-redundant.mir
waitcnt-permute.mir
waitcnt-preexisting.mir
[AMDGPU] gfx1010 VMEM and SMEM implementation
2019-04-30 22:08:23 +00:00
waitcnt-vscnt.ll
[AMDGPU] gfx1010 wait count insertion
2019-05-03 21:53:53 +00:00
waitcnt.mir
AMDGPU: Look through bundles for existing waitcnts
2019-07-03 00:30:44 +00:00
wave32.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
wave_dispatch_regs.ll
widen_extending_scalar_loads.ll
widen-smrd-loads.ll
[DAG] Refactor DAGCombiner::ReassociateOps
2019-04-29 17:50:10 +00:00
widen-vselect-and-mask.ll
wqm.ll
Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"
2019-08-12 14:23:13 +00:00
wqm.mir
write_register.ll
write-register-vgpr-into-sgpr.ll
wrong-transalu-pos-fix.ll
wwm-reserved.ll
AMDGPU: Decompose all values to 32-bit pieces for calling conventions
2019-07-19 13:57:44 +00:00
xfail.r600.bitcast.ll
xnor.ll
xor3-i1-const.ll
[AMDGPU] Fixed handling of imemdiate i1 literals
2019-05-14 16:18:00 +00:00
xor3.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
xor_add.ll
[AMDGPU] gfx1010 core wave32 changes
2019-06-20 15:08:34 +00:00
xor.ll
zero_extend.ll
zext-i64-bit-operand.ll
zext-lid.ll
[AMDGPU] Packed thread ids in function call ABI
2019-06-28 01:52:13 +00:00
