RPCS3/llvm
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm.git synced 2026-07-18 13:16:24 -04:00
Code Issues Packages Projects Releases 10 Wiki Activity

[NFC][SimplifyCFG] 'Safely extract low bits' pattern will also benefit from -phi-node-folding-threshold=3

Browse Source 
This is the naive implementation of x86 BZHI/BEXTR instruction:
it takes input and bit count, and extracts low nbits up to bit width.
I.e. unlike shift it does not have any UB when nbits >= bitwidth.
Which means we don't need a while PHI here, simple select will do.
And if it's a select, it should then be trivial to fix codegen
to select it to BEXTR/BZHI.

See https://bugs.llvm.org/show_bug.cgi?id=34704

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@370369 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Roman Lebedev
2019-08-29 14:46:49 +00:00
parent e9ad855768
commit b71bcdb26c
1 changed files with 35 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
test/Transforms/SimplifyCFG/safe-low-bit-extract.ll
+35
View File
@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -simplifycfg -S | FileCheck %s
; This is the naive implementation of x86 BZHI/BEXTR instruction:
; it takes input and bit count, and extracts low nbits up to bit width.
; I.e. unlike shift it does not have any UB when nbits >= bitwidth.
; Which means we don't need a while PHI here, simple select will do.
define i32 @extract_low_bits(i32 %input, i32 %nbits) {
; CHECK-LABEL: @extract_low_bits(
; CHECK-NEXT: begin:
; CHECK-NEXT: [[SHOULD_MASK:%.*]] = icmp ult i32 [[NBITS:%.*]], 32
; CHECK-NEXT: br i1 [[SHOULD_MASK]], label [[PERFORM_MASKING:%.*]], label [[END:%.*]]
; CHECK: perform_masking:
; CHECK-NEXT: [[MASK_NOT:%.*]] = shl nsw i32 -1, [[NBITS]]
; CHECK-NEXT: [[MASK:%.*]] = xor i32 [[MASK_NOT]], -1
; CHECK-NEXT: [[MASKED:%.*]] = and i32 [[MASK]], [[INPUT:%.*]]
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: [[RES:%.*]] = phi i32 [ [[MASKED]], [[PERFORM_MASKING]] ], [ [[INPUT]], [[BEGIN:%.*]] ]
; CHECK-NEXT: ret i32 [[RES]]
;
begin:
%should_mask = icmp ult i32 %nbits, 32
br i1 %should_mask, label %perform_masking, label %end
perform_masking: ; preds = %begin
%mask.not = shl nsw i32 -1, %nbits
%mask = xor i32 %mask.not, -1
%masked = and i32 %mask, %input
br label %end
end: ; preds = %perform_masking, %begin
%res = phi i32 [ %masked, %perform_masking ], [ %input, %begin ]
ret i32 %res
}