129182 Commits

Author SHA1 Message Date
Sanjay Patel
002b8db36a reorganize llc checks script to allow more flexibility, part 2; NFCI
The goal is to enhance this script to be used with opt and clang:
Break 'main' into functions and change variable names to be more
generic because we want to handle more than x86 asm output.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264307 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 17:15:42 +00:00
Rafael Espindola
9d3b0b6716 Fix gold tests for llvm-readobj format change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264306 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:45:41 +00:00
Simon Pilgrim
1ae39fa1a5 [X86][XOP] Fixed instruction postfixes to more closely match operands
Suggested by Sanjay in D18189 as the multiple folding options in XOP instructions can be tricky

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264305 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:31:30 +00:00
Duncan P. N. Exon Smith
964230413e BitcodeWriter: Move abbreviation for GenericDINode; almost NFC
Simplify ValueEnumerator and WriteModuleMetadata by shifting the logic
for the METADATA_GENERIC_DEBUG abbreviation into WriteGenericDINode.
(This is just like r264302, but for GenericDINode.)

The only change is that the abbreviation is emitted later in the
bitcode, just before the first `GenericDINode` record.  This shouldn't
be observable though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264303 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:30:18 +00:00
Duncan P. N. Exon Smith
3601e72b2a BitcodeWriter: Move abbreviation for DILocation; almost NFC
Simplify ValueEnumerator and WriteModuleMetadata by shifting the logic
for the METADATA_LOCATION abbreviation into WriteDILocation.

The only change is that the abbreviation is emitted later in the
bitcode, just before the first `DILocation` record.  This shouldn't be
observable though.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264302 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:25:51 +00:00
Duncan P. N. Exon Smith
7c9efaa654 BitcodeWriter: Split out named metadata; almost NFC
Split writeNamedMetadata out of WriteModuleMetadata to write named
metadata, and createNamedMetadataAbbrev for the abbreviation.

There should be no effective functionality change, although the layout
of the bitcode will change.  Previously, the abbreviation was emitted at
the top of the block, but now it is delayed until immediately before the
named metadata records are emitted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264301 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:16:08 +00:00
Simon Atanasyan
cc6b0d4dd4 [llvm-readobj] Decode st_other symbol's flags
The patch supports common STV_xxx visibility flags and MIPS specific
STO_MIPS_xxx flags.

Differential Revision: http://reviews.llvm.org/D18447

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264300 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:10:37 +00:00
Duncan P. N. Exon Smith
adb3b8dcbf Bitcode: Module* -> Module&, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264299 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 16:01:46 +00:00
Elena Demikhovsky
56d2e27939 AVX-512: Generate KTEST instead of TEST fir i1 vectors
KTEST instruction may be used instead of TEST in this case:

%int_sel3 = bitcast <8 x i1> %sel3 to i8
%res = icmp eq i8 %int_sel3, zeroinitializer
br i1 %res, label %L2, label %L1

Differential Revision: http://reviews.llvm.org/D18444



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264298 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:53:45 +00:00
NAKAMURA Takumi
89b695a240 ErrorTest.cpp: Move instantiations out of anonymous namespace. gcc didn't complain.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264297 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:40:46 +00:00
Tim Northover
53308b846f CodeGen: extend RHS when splitting ATOMIC_CMP_SWAP_WITH_SUCCESS.
If the operation's type has been promoted during type legalization, we
need to account for the fact that the high bits of the comparison
operand are likely unspecified.

The LHS is usually zero-extended, but MIPS sign extends it, so we have
to be slightly careful.

Patch by Simon Dardis.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264296 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:38:38 +00:00
Tom Stellard
53598f2a0d AMDGPU/SI: Add Polaris support
Patch By: Sonny Jiang

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264295 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:31:05 +00:00
Simon Pilgrim
d531b13c19 [X86][XOP] Merged 128/256 bit 4op instruction definitions. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264294 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:28:02 +00:00
NAKAMURA Takumi
389c434b57 Define ErrorInfo::ID explicitly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264293 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:26:43 +00:00
Rafael Espindola
c0521dd4a2 Fix another case where we were unconditionally linking linkonce GVs.
With this I think that now llvm-link,  lld and the gold plugin should
agree on which symbol is kept.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264292 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:23:01 +00:00
NAKAMURA Takumi
ca458d6ebb Error.cpp: Fix a warning. [-Wpedantic]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264291 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:19:39 +00:00
NAKAMURA Takumi
f043736d85 ErrorTest.cpp: Fix an expression, possibly typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264290 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 15:19:22 +00:00
Rafael Espindola
87fa43be91 Fix resolution of linkonce symbols in comdats.
After comdat processing, the symbols still go through regular symbol
resolution.

We were not doing it for linkonce symbols since they are lazy linked.

This fixes pr27044.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264288 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 14:58:44 +00:00
Daniel Sanders
f7a07617aa [mips] Range check vsplat_simm5 and vsplat_simm10
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18177


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264287 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 14:53:40 +00:00
Pirama Arumuga Nainar
84db1ccc7a Remove unsafe AssertZext after promoting result of FP_TO_FP16
Summary:
Some target lowerings of FP_TO_FP16, for instance ARM's vcvtb.f16.f32
instruction, do not guarantee that the top 16 bits are zeroed out.
Remove the unsafe AssertZext and add tests to exercise this.

Reviewers: jmolloy, sbaranga, kristof.beyls, aadg

Subscribers: llvm-commits, srhines, aemerson

Differential Revision: http://reviews.llvm.org/D18426

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264285 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 14:06:03 +00:00
Nemanja Ivanovic
c4a24ae263 [PowerPC] Disable direct moves for extractelement and bitcast in 32-bit mode
This patch corresponds to review:
http://reviews.llvm.org/D17711

It disables direct moves on these operations in 32-bit mode since the patterns
assume 64-bit registers. The final patch is slightly different from the
Phabricator review as the bitcast operations needed to be disabled in 32-bit
mode as well. This fixes PR26617.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264282 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 13:40:33 +00:00
Amjad Aboud
dbe22520b6 Recommitted r263424 "Supporting all entities declared in lexical scope in LLVM debug info."
After fixing PR26942 (the fix is included in this commit).

Differential Revision: http://reviews.llvm.org/D18350


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264280 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 13:30:16 +00:00
Daniel Sanders
da7ce1c8eb [mips] Range check simm10
Summary:

Reviewers: vkalintiris

Subscribers: llvm-commits, dsanders

Differential Revision: http://reviews.llvm.org/D18148


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264279 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 13:26:59 +00:00
Simon Pilgrim
b4ecd3cfe6 [X86][XOP] Support for VPPERM byte shuffle instruction
This patch begins adding support for lowering to the XOP VPPERM instruction - adding the X86ISD::VPPERM opcode.

Differential Revision: http://reviews.llvm.org/D18189

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264260 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 11:52:43 +00:00
Daniel Sanders
74591f1a32 [mips] Tidy up cnMIPS tablegen definitions. NFC.
Summary:
In particular, make the cnMIPS predicates much more obvious and prefer
  def ... : ... {
    let Foo = bar;
  }
over:
  let Foo = bar in
  def ... : ...;

Reviewers: vkalintiris

Subscribers: dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D18354

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264258 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 11:40:48 +00:00
Vasileios Kalintiris
26bfbf7c8d Fix sequence point warning. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264255 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 10:53:28 +00:00
James Molloy
66d1cd5130 [llvm-nm] Fix r264247
I committed the test changes successfully but managed to miss the actual code change! (lack of git -a)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264249 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 09:23:51 +00:00
Zlatko Buljan
48945fb1c0 [mips][microMIPS] Add CodeGen support for DIV, MOD, DIVU, MODU, DDIV, DMOD, DDIVU and DMODU instructions
Differential Revision: http://reviews.llvm.org/D17137


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264248 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 09:22:45 +00:00
James Molloy
d49b347df5 [llvm-nm] Correct -P ELF output
Correctly add a space between the address and size when outputting in posix mode (-P).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264247 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 09:18:09 +00:00
Hrvoje Varga
405224b9ee [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions
Differential Revision: http://reviews.llvm.org/D17328


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264246 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 08:02:09 +00:00
Hrvoje Varga
a00edb5096 [mips][microMIPS] Fix for "Cannot copy registers" assertion
Differential Revision: http://reviews.llvm.org/D17068


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264245 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 06:05:35 +00:00
Adam Nemet
8b742a005a [LAA] Formatting fix in previous change
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264244 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 05:15:24 +00:00
Adam Nemet
7cacf39c01 [LAA] Support memchecks involving loop-invariant addresses
We used to only allow SCEVAddRecExpr for pointer expressions in order to
be able to compute the bounds.  However this is also trivially possible
for loop-invariant addresses (scUnknown) since then the bounds are the
address itself.

Interestingly, we used allow this for the special case when the
loop-invariant address happens to also be an SCEVAddRecExpr (in an outer
loop).

There are a couple more loops that are vectorized in SPEC after this.
My guess is that the main reason we don't see more because for example a
loop-invariant load is vectorized into a splat vector with several
vector-inserts.  This is likely to make the vectorization unprofitable.
I.e. we don't notice that a later LICM will move all of this out of the
loop so the cost estimate should really be 0.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264243 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 04:28:47 +00:00
Lang Hames
d1800c2b1c [Support] Add conversions between Expected<T> and ErrorOr<T>.
More utilities to help with std::error_code -> Error transitions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264238 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 02:00:10 +00:00
Kostya Serebryany
c09d592889 [libFuzzer] don't report memory leaks if we are dying due to a timeout (just use _Exit instead of exit in the timeout callback)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264237 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 01:32:08 +00:00
Kostya Serebryany
f4b00d0631 [libFuzzer] use fdopen+vfprintf instead of fsnprintf+write
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264230 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 00:57:32 +00:00
Simon Pilgrim
5385e47f44 [X86][SSE] Added tests to ensure that consecutive loads including any/all volatiles are not combined
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264225 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 00:14:37 +00:00
Paul Robinson
d0c6d209f8 [PS4] Guarantee an instruction after a 'noreturn' call.
We need the "return address" of a noreturn call to be within the
bounds of the calling function; TrapUnreachable turns 'unreachable'
into a 'ud2' instruction, which has that desired effect.

Differential Revision: http://reviews.llvm.org/D18414


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264224 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 00:10:03 +00:00
Rafael Espindola
6f5ddf8965 Fix lazy linking of comdat members.
If not for lazy linking of linkonce GVs, comdats are just a
preprocessing before symbol resolution.

Lazy linking complicates it since when we pick a visible member of
comdat, we have to make sure the rest of it passes symbol resolution
too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264223 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 00:06:03 +00:00
Mike Aizatsky
9647ee51e2 [sancov] -print-coverage-stats option to print various coverage statistics.
Differential Revision: http://reviews.llvm.org/D18418

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264222 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-24 00:00:08 +00:00
Lang Hames
d34f785662 [Support] Make all Errors convertible to std::error_code.
This is a temporary crutch to enable code that currently uses std::error_code
to be incrementally moved over to Error. Requiring all Error instances be
convertible enables clients to call errorToErrorCode on any error (not just
ECErrors created by conversion *from* an error_code).

This patch also moves code for Error from ErrorHandling.cpp into a new
Error.cpp file.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264221 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 23:57:28 +00:00
Matt Arsenault
b883372896 APFloat: Fix signalling nans for scalbn
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264219 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 23:51:45 +00:00
Matt Arsenault
54f7128a27 AMDGPU: Remove atomic inc/dec patterns
There is no benefit to these since materializing the constant 1
requires the same number of instructions as materializing uint_max

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264215 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 23:23:38 +00:00
Matt Arsenault
fc80e900d8 AMDGPU: Promote alloca should skip volatiles
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264214 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 23:17:29 +00:00
Mike Aizatsky
bbc99ea0f8 [sancov] code readability improvement.
Summary: Reply to http://reviews.llvm.org/D18341

Differential Revision: http://reviews.llvm.org/D18406

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264213 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 23:15:03 +00:00
Justin Bogner
8b620f3783 docs: Fix a missing language in a code-block
This should fix the docs build.
Spotted by spstarr, thanks!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264209 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 22:54:19 +00:00
Justin Lebar
fe3378bb83 [CUDA] Update docs to reflect that we no longer define __NVCC__.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264208 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 22:43:10 +00:00
Pete Cooper
552f3d8472 StringRef::copy shouldn't allocate anything for length 0 strings.
The BumpPtrAllocator currently doesn't handle zero length allocations well.
The discussion for how to fix that is ongoing.  However, there's no need
for StringRef::copy to actually allocate anything here anyway, so just
return StringRef() when we get a zero length copy.

Reviewed by David Blaikie

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264201 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 21:49:31 +00:00
Matt Arsenault
222f9e97f6 AMDGPU: Insert moves of frame index to value operands
Strengthen tests of storing frame indices.

Right now this just creates irrelevant scheduling changes.

We don't want to have multiple frame index operands
on an instruction. There seem to be various assumptions
that at least the same frame index will not appear twice
in the LocalStackSlotAllocation pass.

There's no reason to have this happen, and it just
makes it easy to introduce bugs where the immediate
offset is appplied to the storing instruction when it should
really be applied to the value being stored as a separate
add.

This might not be sufficient. It might still be problematic
to have an add fi, fi situation, but that's even less unlikely
to happen in real code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264200 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 21:49:25 +00:00
Cong Hou
58aed69858 Allow X86::COND_NE_OR_P and X86::COND_NP_OR_E to be reversed.
Currently, AnalyzeBranch() fails non-equality comparison between floating points
on X86 (see https://llvm.org/bugs/show_bug.cgi?id=23875). This is because this
function can modify the branch by reversing the conditional jump and removing
unconditional jump if there is a proper fall-through. However, in the case of
non-equality comparison between floating points, this can turn the branch
"unanalyzable". Consider the following case:

jne.BB1
jp.BB1
jmp.BB2
.BB1:
...
.BB2:
...

AnalyzeBranch() will reverse "jp .BB1" to "jnp .BB2" and then "jmp .BB2" will be
removed:

jne.BB1
jnp.BB2
.BB1:
...
.BB2:
...

However, AnalyzeBranch() cannot analyze this branch anymore as there are two
conditional jumps with different targets. This may disable some optimizations
like block-placement: in this case the fall-through behavior is enforced even if
the fall-through block is very cold, which is suboptimal.

Actually this optimization is also done in block-placement pass, which means we
can remove this optimization from AnalyzeBranch(). However, currently
X86::COND_NE_OR_P and X86::COND_NP_OR_E are not reversible: there is no defined
negation conditions for them.

In order to reverse them, this patch defines two new CondCode X86::COND_E_AND_NP
and X86::COND_P_AND_NE. It also defines how to synthesize instructions for them.
Here only the second conditional jump is reversed. This is valid as we only need
them to do this "unconditional jump removal" optimization.


Differential Revision: http://reviews.llvm.org/D11393




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@264199 91177308-0d34-0410-b5e6-96231b3b80d8
2016-03-23 21:45:37 +00:00