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Author SHA1 Message Date
Akira Hatanaka
0917ca56dc [mips] Fix typos. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190236 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 01:14:42 +00:00
Akira Hatanaka
3e6758541b [mips] Enhance command line option "-mno-ldc1-sdc1" to expand base+index double 
precision loads and stores as well as reg+imm double precision loads and stores.

Previously, expansion of loads and stores was done after register allocation,
but now it takes place during legalization. As a result, users will see double
precision stores and loads being emitted to spill and restore 64-bit FP registers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190235 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:52:30 +00:00
Akira Hatanaka
d65d2fde4e [mips] Place parentheses around && to silence warning. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190234 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:26:26 +00:00
Richard Smith
9401181aed Remove verifier check that attribute 'builtin' is only applied to calls to 
functions marked 'nobuiltin'. That approach doesn't play well with LTO, and
there's no harm in marking a call as 'builtin' if it was going to be a builtin
regardless.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190233 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:25:48 +00:00
Akira Hatanaka
1abf0afdd4 [mips] Add definition of instruction "drotr32" (double rotate right plus 32). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190232 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:18:01 +00:00
Manman Ren
0e85f6e391 Debug Info: Use identifier to reference DIType in containing type field of 
a DISubprogram.
    
Verifier is updated accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190229 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:04:05 +00:00
Akira Hatanaka
69f8e0935a [mips] Use uimm5 and uimm6 instead of shamt and imm, if the immediate has to fit 
into a 5-bit or 6-bit field.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190226 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-07 00:02:02 +00:00
Manman Ren
8b56ca61e1 Debug Info: pass in VTableHolder as DIType instead of MDNode *. 
Remove one cast and improve readability. No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190225 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:54:23 +00:00
Akira Hatanaka
997c5dead8 [mips] Define "trap" as a pseudo instruction that turns into "break 0, 0". 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190224 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:52:46 +00:00
Akira Hatanaka
cd3c1b9af9 [mips] Delete unused classes and defs. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190221 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:42:58 +00:00
Akira Hatanaka
1d04ca7987 [mips] Make "b" (unconditional branch) a pseudo. "b" is an assembly idiom, which is 
equivalent to "beq $zero, $zero, offset".




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190220 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:40:15 +00:00
Akira Hatanaka
77e1ebd18f [mips] Set instruction itineraries of loads, stores and conditional moves. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190219 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 23:28:24 +00:00
Manman Ren
0b3d39235a TBAA: add isTBAAVtableAccess to MDNode so clients can call the function 
instead of having its own implementation.

The implementation of isTBAAVtableAccess is in TypeBasedAliasAnalysis.cpp
since it is related to the format of TBAA metadata.

The path for struct-path tbaa will be exercised by
test/Instrumentation/ThreadSanitizer/read_from_global.ll, vptr_read.ll, and
vptr_update.ll when struct-path tbaa is on by default.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190216 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 22:47:05 +00:00
Manman Ren
1307103dff Debug Info Testing: updated to use NULL instead of "i32 0" in a few fields. 
Field 2 of DIType (Context), field 9 of DIDerivedType (TypeDerivedFrom),
field 12 of DICompositeType (ContainingType), fields 2, 7, 12 of DISubprogram
(Context, Type, ContainingType).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190205 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 21:03:58 +00:00
Aaron Watry
546dcc5ddc R600: Add support for LDS atomic subtract 
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190200 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 20:17:42 +00:00
Manman Ren
e42279cda4 Debug Info: Use identifier to reference DIType in containing type field of 
a DICompositeType.
    
Verifier is updated accordingly.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190190 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 18:46:00 +00:00
Manman Ren
5930eabe0f Debug Info: Move a helper function getTypeIdentifier from DIBuilder to be part 
of DIType.
    
Implement DIType::generateRef to return a type reference. This function will be
used in setContaintingType and in DIBuilder to generete the type reference.
    
No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190188 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 18:27:00 +00:00
Manman Ren
28da141d44 Debug Info Testing: Updated to use null instead of "i32 0" for containing-type 
field of DICompositeType.

This will help the follow-on patch of using DITypeRef for containing-type field.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190187 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 18:13:59 +00:00
Adrian Prantl
4f1e5fba41 debuginfo-tests: Add support for an lldb wrapper script 
to be used on darwin in lieu of gdb.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190186 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 18:12:01 +00:00
Andrew Trick
fb386db636 mi-sched: cleanup register pressure update, remove a FIXME. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190181 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:32:47 +00:00
Andrew Trick
6bf0c6c535 mi-sched: improve regpressure tracing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:32:44 +00:00
Andrew Trick
fd30312c49 mi-sched: print tree size in -view-misched-dags 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190179 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:32:42 +00:00
Andrew Trick
1251bcccc1 mi-sched: register pressure update tracing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190178 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:32:39 +00:00
Andrew Trick
f9c2fa8341 mi-sched: Reorder Cyclicpath (latency) and CriticalMax (pressure) heuristics. 
The latency based scheduling could induce spills in some cases.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190177 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:32:36 +00:00
Andrew Trick
38e61122f2 Added MachineSchedPolicy. 
Allow subtargets to customize the generic scheduling strategy.
This is convenient for targets that don't need to add new heuristics
by specializing the strategy.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190176 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:32:34 +00:00
Hans Wennborg
1bcff6cffa msbuild integration: provide separate files for VS2010 and VS2012 
The previous msbuild integration only worked if VS2010 was installed. This patch
renames the current integration to LLVM-vs2010 and adds LLVM-vs2012.

Differential Revision: http://llvm-reviews.chandlerc.com/D1614

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190173 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 17:05:46 +00:00
Matthias Braun
b63db85350 avoid unnecessary direct access to LiveInterval::ranges 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190170 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 16:44:32 +00:00
Matthias Braun
1920156982 remove unused argument from LiveRanges::join() 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190169 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 16:44:29 +00:00
Matthias Braun
2d5558cbae remove pointless assert 
The if above it ensures the property anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190168 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 16:44:27 +00:00
Matthias Braun
c725865bbc fix comment 
There's no 'B3' in the example.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190167 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 16:44:25 +00:00
Matthias Braun
256cb9eaaf fix typo in comment 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190165 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 16:19:22 +00:00
Daniel Sanders
a86062c4b1 [mips][msa] Indentation 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190156 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:25:06 +00:00
Daniel Sanders
5cb39b22fb [mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance 
Tested with 'llvm-tblgen -print-records' which outputs identical records before
and after this patch.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190155 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:15:05 +00:00
Vladimir Medic
638382e6f1 This patch adds support for microMIPS Multiply and Add/Sub instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190154 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:08:00 +00:00
Daniel Sanders
3aaa3e31aa [mips][msa] Made the operand register sets optional for the VEC formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190153 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 13:01:47 +00:00
Vladimir Medic
dadd1fba32 This patch adds support for microMIPS Move to/from HI/LO instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190152 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:53:21 +00:00
Daniel Sanders
9e935a77a5 [mips][msa] Made the operand register sets optional for the ELM_INSVE formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190151 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:50:52 +00:00
Daniel Sanders
b9987d1aa1 [mips][msa] Made the operand register sets optional for the 3RF_4RF format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190150 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:44:13 +00:00
Vladimir Medic
bf7f7b5e0e This patch adds support for microMIPS Move Conditional instructions. Test cases are included in patch. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190148 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:41:17 +00:00
Tim Northover
a5eeb9da05 SelectionDAG: create correct BooleanContent constants 
Occasionally DAGCombiner can spot that a SETCC operation is completely
redundant and reduce it to "all true" or "all false". If this happens to a
vector, the value produced has to take account of what a normal comparison
would have produced, which may be an all-1s bitmask.

The fix in SelectionDAG.cpp is tested, however, as far as I can see the code in
TargetLowering.cpp is possibly unreachable and almost certainly irrelevant when
triggered so there are no tests. However, I believe it's still clearly the
right change and may save someone else some hassle if it suddenly becomes
reachable. So I'm doing it anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190147 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:38:12 +00:00
Daniel Sanders
888497d8a2 [mips][msa] Made the operand register sets optional for the 3RF formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190146 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:32:57 +00:00
Daniel Sanders
6976d75415 [mips][msa] Made the operand register sets optional for the 3R_4R format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190145 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:30:43 +00:00
Vladimir Medic
a674463aac This patch adds support for microMIPS disassembler and disassembler make check tests. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190144 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:30:36 +00:00
Daniel Sanders
99d02d1325 [mips][msa] Made the operand register sets optional for the 2RF format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190143 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:28:13 +00:00
Daniel Sanders
d31c238372 [mips][msa] Made the operand register sets optional for the I8 format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190142 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:25:47 +00:00
Daniel Sanders
7d3da67611 [mips][msa] Made the operand register sets optional for the I5 and SI5 formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190141 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:23:19 +00:00
Daniel Sanders
bfb9bab243 [mips][msa] Made the operand register sets optional for the BIT_[BHWD] formats 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190140 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 12:10:24 +00:00
Richard Sandiford
aff1c6427c [SystemZ] Tweak integer comparison code 
The architecture has many comparison instructions, including some that
extend one of the operands.  The signed comparison instructions use sign
extensions and the unsigned comparison instructions use zero extensions.
In cases where we had a free choice between signed or unsigned comparisons,
we were trying to decide at lowering time which would best fit the available
instructions, taking things like extension type into account.  The code
to do that was getting increasingly hairy and was also making some bad
decisions.  E.g. when comparing the result of two LLCs, it is better to use
CR rather than CLR, since CR can be fused with a branch while CLR can't.

This patch removes the lowering code and instead adds an operand to
integer comparisons to say whether signed comparison is required,
whether unsigned comparison is required, or whether either is OK.
We can then leave the choice of instruction up to the normal isel code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190138 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 11:51:39 +00:00
Daniel Sanders
e3273b3275 [mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size 
No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190134 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 11:01:38 +00:00
Daniel Sanders
cc538affd2 [mips][msa] Made the operand register sets optional for the 3R format 
Their default is to be the same as the result register set.

No functional change



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190133 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-09-06 10:59:24 +00:00