144658 Commits

Author SHA1 Message Date
Wolfgang Pieb
0956efb856 DebugInfo: Track spilled variables in LiveDebugValues
When variables are spilled to the stack by the register allocator, keep track of their
debug locations in LiveDebugValues and insert DBG_VALUE instructions at the appropriate
place. Ensure that the locations are propagated down the dominator tree via the existing 
mechanisms.

Reviewer: aprantl

Differential Revision: https://reviews.llvm.org/D29500


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294356 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 21:23:15 +00:00
Kevin Enderby
b1b66d4aca Fix a typo in an error message for a check of invalid Mach-O files where
it was printing the field name fileoff instead of filesize.  The original check
was added in r278557.

This was found in tracking down the problem that lead to the fix in
r293842 - [dsymutil] Fix __LINKEDIT vmsize in dsymutil upgrade path

rdar://30386075


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294354 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 21:20:44 +00:00
Daniel Berlin
94f2e5a1f1 Add PredicateInfo utility and printing pass
Summary:
This patch adds a utility to build extended SSA (see "ABCD: eliminating
array bounds checks on demand"), and an intrinsic to support it. This
is then used to get functionality equivalent to propagateEquality in
GVN, in NewGVN (without having to replace instructions as we go). It
would work similarly in SCCP or other passes. This has been talked
about a few times, so i built a real implementation and tried to
productionize it.

Copies are inserted for operands used in assumes and conditional
branches that are based on comparisons (see below for more)

Every use affected by the predicate is renamed to the appropriate
intrinsic result.

E.g.
%cmp = icmp eq i32 %x, 50
br i1 %cmp, label %true, label %false
true:
ret i32 %x
false:
ret i32 1

will become

%cmp = icmp eq i32, %x, 50
br i1 %cmp, label %true, label %false
true:
; Has predicate info
; branch predicate info { TrueEdge: 1 Comparison: %cmp = icmp eq i32 %x, 50 }
%x.0 = call @llvm.ssa_copy.i32(i32 %x)
ret i32 %x.0
false:
ret i23 1

(you can use -print-predicateinfo to get an annotated-with-predicateinfo dump)

This enables us to easily determine what operations are affected by a
given predicate, and how operations affected by a chain of
predicates.

Reviewers: davide, sanjoy

Subscribers: mgorny, llvm-commits, Prazek

Differential Revision: https://reviews.llvm.org/D29519

Update for review comments

Fix a bug Nuno noticed where we are giving information about and/or on edges where the info is not useful and easy to use wrong

Update for review comments

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294351 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 21:10:46 +00:00
Duncan P. N. Exon Smith
98516248d0 ADT: Add explicit conversions for reverse ilist iterators
Add explicit conversions between forward and reverse ilist iterators.
These follow the conversion conventions of std::reverse_iterator, which
are off-by-one: the newly-constructed "reverse" iterator dereferences to
the previous node of the one sent in.  This has the benefit of
converting reverse ranges in place:
  - If [I, E) is a valid range,
  - then [reverse(E), reverse(I)) gives the same range in reverse order.

ilist_iterator::getReverse() is unchanged: it returns a reverse iterator
to the *same* node.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294349 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 21:03:50 +00:00
Hans Wennborg
34a6e0d36a [X86] Disable conditional tail calls (PR31257)
They are currently modelled incorrectly (as calls, which clobber
registers, confusing e.g. Machine Copy Propagation).

Reverting until we figure out the proper solution.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294348 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 20:37:45 +00:00
Sanjoy Das
9ac774d7cf Fix the docs build
(and add a bit of formatting.)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294347 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 20:36:03 +00:00
Tim Northover
dabb7fcdd6 GlobalISel: translate @llvm.va_end intrinsic.
Turns out no-one actually cares about this one (at least) in tree so we can
just drop it entirely.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294345 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 20:08:59 +00:00
Sanjay Patel
04827a7eed [x86] improve comments for SHRUNKBLEND node creation; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294344 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:54:16 +00:00
Matthew Simpson
9e8cc9ccc4 [LV] Add new ARM/AArch64 interleaved access cost model tests (NFC)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294342 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:34:24 +00:00
Daniel Berlin
f2da6f93fe This patch adds a ssa_copy intrinsic, as part of splitting up D29316.
Summary:
The intrinsic, marked as returning it's first argument, has no code
generation effect (though currently not every optimization pass knows
that intrinsics with the returned attribute can be looked through).

It is about to be used to by the PredicateInfo pass to attach
predicate information to existing operands, and be able to tell what
the predicate information affects.

We deliberately do not attach any info through a second operand so
that the intrinsics do not need to dominate the comparisons/etc (since
in the case of assume, we may want to push them up the post-dominator
tree).

Reviewers: davide, sanjoy

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29517

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294341 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:29:25 +00:00
Daniel Berlin
e851e52838 Replace custom written DFS walk with depth first iterator
Summary:
GenericDomTreeConstruction had its own written DFS walk.
It is basically identical to the DFS walk df_* is doing in the iterators.
the one difference is that df_iterator uses an internal visited set.
The GenericDomTreeConstruction one reused a field in an existing densemap lookup.

Time-wise, this way is actually more cache-friendly (the previous way has a random store
into a successor's info, the new way does that store at the same time and in the same place
as other stores to the same info)

It costs some very small amount of memory to do this, and one we pay in some other part of
dom tree construction *anyway*, so we aren't really increasing dom tree constructions's
peak memory usage.

It could still be changed to use the old field with a little work on df_ext_* if we care
(and if someone find performance regressions)

Reviewers: chandlerc

Reviewed By: chandlerc

Subscribers: Eugene.Zelenko, llvm-commits

Differential Revision: https://reviews.llvm.org/D8932

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294339 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:24:26 +00:00
Sanjoy Das
a0be0b1390 [ImplicitNullCheck] Extend Implicit Null Check scope by using stores
Summary:
This change allows usage of store instruction for implicit null check.

Memory Aliasing Analisys is not used and change conservatively supposes
that any store and load may access the same memory. As a result
re-ordering of store-store, store-load and load-store is prohibited.

Patch by Serguei Katkov!

Reviewers: reames, sanjoy

Reviewed By: sanjoy

Subscribers: atrick, llvm-commits

Differential Revision: https://reviews.llvm.org/D29400

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294338 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:19:49 +00:00
Sanjay Patel
27341a9e0b [x86] use range-for loops; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294337 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:18:25 +00:00
Matthew Simpson
85dcf5ecdf [LV] Simplify ARM/AArch64 interleaved access cost model tests (NFC)
This patch removes unneeded instructions from the existing ARM/AArch64
interleaved access cost model tests. I'll be adding a similar set of tests in a
follow-on patch to increase coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294336 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:17:44 +00:00
Chris Bieneman
d2206e4788 [CMake] Move ninja job pool options to HandleLLVMOptions
Moving the Ninja job pool configuration settings into the HandleLLVMOptions module will allow standalone builds of LLVM sub-projects to use the LLVM options without needing to re-implement them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294334 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:06:22 +00:00
Sanjay Patel
6271cac448 [x86] use getSignBit() for clarity; NFCI
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294333 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 19:01:35 +00:00
David Blaikie
d1bd111c03 Fix the -Werror build for some sign-comparisons
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294331 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 18:58:17 +00:00
Nemanja Ivanovic
c44f1880c9 [PowerPC][Altivec] Add vnot extended mnemonic
Adds the vnot extended mnemonic for the vnor instruction.

Committing on behalf of brunoalr (Bruno Rosa).

Differential Revision: https://reviews.llvm.org/D29225


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294330 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 18:57:29 +00:00
Reid Kleckner
e975b155eb [SDAGISel] Simplify some SDAGISel code, NFC
Hoist entry block code for arguments and swift error values out of the
basic block instruction selection loop. Lowering arguments once up front
seems much more readable than doing it conditionally inside the loop. It
also makes it clear that argument lowering can update StaticAllocaMap
because no instructions have been selected yet.

Also use range-based for loops where possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294329 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 18:42:53 +00:00
Pavel Labath
6997bd2426 Attempt to fix MSVC build broken by r294326
MSVC does not think that `char []` can be constexpr. Switch to regular const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294327 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 18:35:36 +00:00
Pavel Labath
6f3190d682 [Support] Add FormatVariadic support for chrono types
Summary:
The formatter has three knobs:
- the user can choose which time unit to use for formatting (default: whatever is the unit of the input)
- he can choose whether the unit gets displayed (default: yes)
- he can affect the way the number itself is formatted via standard number formatting options (default:default)

Reviewers: zturner, inglorion

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D29481

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294326 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 18:11:33 +00:00
Sanjay Patel
a1d2453472 [TargetLowering] fix formatting and comments for ShrinkDemandedConstant; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294325 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 18:04:26 +00:00
Alexander Timofeev
ce06d9cb99 [AMDGPU] Fix for SIMachineScheduler crash. SI Scheduler should track
lane masks.

	 Differential revision: https://reviews.llvm.org/D29442

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294324 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:57:48 +00:00
Davide Italiano
4b54eb2c37 [InstCombine] Make max size array combine a tunable.
Requested by Sanjoy/Hal a while ago, and forgotten by me
(r283612).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294323 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:56:50 +00:00
Krzysztof Parzyszek
051dda606b [Hexagon] Update instruction types
Remove TypeXTYPE, TypeALU32, TypeSYSTEM, TypeJR, and instead use their
architecture counterparts.

Patch by Colin LeMahieu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294321 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:47:37 +00:00
Krzysztof Parzyszek
ab8079ed2a [Hexagon] Remove encoding bits from mapped instructions
- Map A2_zxtb to A2_andir.
- Map PS_call_nr J2_call.
- Map A2_tfr[t|f][new] to A2_padd[t|f][new].
    
Patch by Colin LeMahieu.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294320 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:42:11 +00:00
Reid Kleckner
4e66158a93 Fix my GVNHoist test case from r294317
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294319 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:35:53 +00:00
Adrian Prantl
04ac0249b0 Fix the bitcode upgrade for DIGlobalVariable in a DIImportedEntity context.
The bitcode upgrade for DIGlobalVariable unconditionally wrapped
DIGlobalVariables in a DIGlobalVariableExpression. When a
DIGlobalVariable is referenced by a DIImportedEntity, however, this is
wrong. This patch fixes the bitcode upgrade by deferring the creation
of DIGlobalVariableExpressions until we know the context of the
DIGlobalVariable.

<rdar://problem/30134279>

Differential Revision: https://reviews.llvm.org/D29349

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294318 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:35:41 +00:00
Reid Kleckner
c1438368aa Revert "[GVNHoist] Merge DebugLoc metadata on hoisted instructions"
This reverts commit r294250. It caused PR31891.

Add a test case that shows that inlinable calls retain location
information with an accurate scope.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294317 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 17:31:13 +00:00
Daniel Berlin
ed9337a488 MemorySSA: Remove unnecessary classof functions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294316 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 16:58:22 +00:00
Simon Pilgrim
cab8418968 [X86][SSE] Ensure that vector shift-by-immediate inputs are correctly bitcast to the result type
vXi8/vXi64 vector shifts are often shifted as vYi16/vYi32 types but we weren't always remembering to bitcast the input.

Tested with a new assert as we don't currently manipulate these shifts enough for test cases to catch them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294308 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 14:22:25 +00:00
Artur Pilipenko
6449f6ff38 Add DAGCombiner load combine tests for {a|s}ext, {a|z|s}ext load nodes
Currently we don't support these nodes, so the tests check the current codegen without load combine. This change makes the review of the change to support these nodes more clear.

Separated from https://reviews.llvm.org/D29591 review.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294305 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 14:09:37 +00:00
Igor Laevsky
5ac65c9c9a [CodeGenPrepare] Hoist all getSubtargetImpl calls to the beginning of the pass
Differential Revision: https://reviews.llvm.org/D29456



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294301 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 13:27:20 +00:00
Simon Pilgrim
108d7ddae3 [X86][SSE] Generalized integer absolute tests to test canonical pattern as well as intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294300 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 13:15:09 +00:00
Christof Douma
5c21be0e40 [ARM] Make RWPI use movw/movt when available
When constructing global address literals while targeting the RWPI
relocation model. LLVM currently only uses literal pools. If MOVW/MOVT
instructions are available we can use these instead. Beside being more
efficient it allows -arm-execute-only to work with
-relocation-model=RWPI as well.

When we generate MOVW/MOVT for global addresses when targeting the RWPI
relocation model, we need to use base relative relocations. This patch
does the needed plumbing in MC to generate these for MOVW/MOVT.

Differential Revision: https://reviews.llvm.org/D29487

Change-Id: I446786e43a6f5aa9b6a5bb2cd216d60d41c7755d

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294298 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 13:07:12 +00:00
Simon Pilgrim
480403fae1 [X86][SSE] Added 256-bit vector tests cases
Exposes some poor codegen with identity shuffle due to bad interaction with insert_subvector(extract_subvector) / concat_subvectors

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294296 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 12:01:36 +00:00
Joey Gouly
f83a9ee2df [APInt] Fix rotl/rotr when the shift amount is greater than the total bit width.
Review: https://reviews.llvm.org/D27749


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294295 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 11:58:22 +00:00
Daniel Jasper
7085bdc3ce Revert "[DAGCombiner] (add X, (adde Y, 0, Carry)) -> (adde X, Y, Carry)"
This reverts commit r294186.

On an internal test, this triggers an out-of-memory error on PPC,
presumably because there is another dagcombine that does the exact
opposite triggering and endless loop consuming more and more memory.

Chandler has started at creating a reduced test case and we'll attach it
as soon as possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294288 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 08:57:50 +00:00
Craig Topper
472303af3a [AVX-512] Add masked and unmasked shift by immediate instructions to load folding tables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294287 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 07:31:00 +00:00
Craig Topper
78b86169a5 [AVX-512] Add masked shift instructions to load folding tables.
This adds the masked versions of everything, but the shift by immediate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294286 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 07:30:57 +00:00
Craig Topper
6e1fdd37ce [AVX-512] Add some of the shift instructions to the load folding tables.
This includes unmasked forms of variable shift and shifting by the lower element of a register.

Still need to do shift by immediate which was not foldable prior to avx512 and all the masked forms.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294285 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 07:30:54 +00:00
Matt Arsenault
566061d5d4 AMDGPU: Fix missing static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294281 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 04:37:59 +00:00
Craig Topper
47db62e175 [X86] Change the Defs list for VZEROALL/VZEROUPPER back to not including YMM16-31.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294277 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 04:10:57 +00:00
Craig Topper
373cbacff0 [AVX-512] Put the integer stack folding tests in alphabetical order.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294276 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 04:10:54 +00:00
Chandler Carruth
869cf60647 [PM] Defend against getting slightly wrong template arguments passed
into CRTP base classes.

This can sometimes happen and not cause an immediate failure when the
derived class is, itself, a template. You can end up essentially calling
methods on the wrong derived type but a type where many things will
appear to "work".

To fail fast and with a clear error message we can use a static_assert,
but we have to stash that static_assert inside a method body or nested
type that won't need to be completed while building the base class. I've
tried to pick a reasonably small number of places that seemed like they
would definitely get triggered on use.

This is the last of the patch series defending against this that I have
planned, so far no bugs other than the original were found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294275 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 03:34:08 +00:00
Peter Collingbourne
8c57d78e93 LowerTypeTests: Simplify. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294273 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 03:20:58 +00:00
Chandler Carruth
e4145c2707 [IR/Analysis] Defend against getting slightly wrong template arguments
passed into CRTP base classes.

This can sometimes happen and not cause an immediate failure when the
derived class is, itself, a template. You can end up essentially calling
methods on the wrong derived type but a type where many things will
appear to "work".

To fail fast and with a clear error message we can use a static_assert,
but we have to stash that static_assert inside a method body or nested
type that won't need to be completed while building the base class. I've
tried to pick a reasonably small number of places that seemed like
reliably places for this to be instantiated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294272 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 03:17:30 +00:00
Chandler Carruth
167cdd001a [ADT] Defend against getting slightly wrong template arguments passed
into CRTP base classes.

This can sometimes happen and not cause an immediate failure when the
derived class is, itself, a template. You can end up essentially calling
methods on the wrong derived type but a type where many things will
appear to "work".

To fail fast and with a clear error message we can use a static_assert,
but we have to stash that static_assert inside a method body or nested
type that won't need to be completed while building the base class. I've
tried to pick a reasonably small number of places that seemed like
reliably places for this to be instantiated.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294271 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 03:15:12 +00:00
Krzysztof Parzyszek
1511b08784 [Hexagon] Address ASAN and UBSAN failures after r294226
Reinstate r294256 with a fix.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294269 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 02:31:53 +00:00
Matthias Braun
91d3cab4fd RegisterCoalescer: Fix joinReservedPhysReg()
joinReservedPhysReg() can only deal with a liverange in a single basic
block when copying from a vreg into a physreg.

See also rdar://30306405

Differential Revision: https://reviews.llvm.org/D29436

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294268 91177308-0d34-0410-b5e6-96231b3b80d8
2017-02-07 01:59:39 +00:00