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Author SHA1 Message Date
Ulrich Weigand
0db5379fe6 [PowerPC] Support compare mnemonics with implied CR0 
Just like for branch mnemonics (where support was recently added), the
assembler is supposed to support extended mnemonics for the compare
instructions where no condition register is specified explicitly
(and CR0 is assumed implicitly).

This patch adds support for those extended compare mnemonics.


Index: llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
===================================================================
--- llvm-head.orig/test/MC/PowerPC/ppc64-encoding-ext.s
+++ llvm-head/test/MC/PowerPC/ppc64-encoding-ext.s
@@ -449,21 +449,37 @@
 
 # CHECK: cmpdi 2, 3, 128                 # encoding: [0x2d,0x23,0x00,0x80]
          cmpdi 2, 3, 128
+# CHECK: cmpdi 0, 3, 128                 # encoding: [0x2c,0x23,0x00,0x80]
+         cmpdi 3, 128
 # CHECK: cmpd 2, 3, 4                    # encoding: [0x7d,0x23,0x20,0x00]
          cmpd 2, 3, 4
+# CHECK: cmpd 0, 3, 4                    # encoding: [0x7c,0x23,0x20,0x00]
+         cmpd 3, 4
 # CHECK: cmpldi 2, 3, 128                # encoding: [0x29,0x23,0x00,0x80]
          cmpldi 2, 3, 128
+# CHECK: cmpldi 0, 3, 128                # encoding: [0x28,0x23,0x00,0x80]
+         cmpldi 3, 128
 # CHECK: cmpld 2, 3, 4                   # encoding: [0x7d,0x23,0x20,0x40]
          cmpld 2, 3, 4
+# CHECK: cmpld 0, 3, 4                   # encoding: [0x7c,0x23,0x20,0x40]
+         cmpld 3, 4
 
 # CHECK: cmpwi 2, 3, 128                 # encoding: [0x2d,0x03,0x00,0x80]
          cmpwi 2, 3, 128
+# CHECK: cmpwi 0, 3, 128                 # encoding: [0x2c,0x03,0x00,0x80]
+         cmpwi 3, 128
 # CHECK: cmpw 2, 3, 4                    # encoding: [0x7d,0x03,0x20,0x00]
          cmpw 2, 3, 4
+# CHECK: cmpw 0, 3, 4                    # encoding: [0x7c,0x03,0x20,0x00]
+         cmpw 3, 4
 # CHECK: cmplwi 2, 3, 128                # encoding: [0x29,0x03,0x00,0x80]
          cmplwi 2, 3, 128
+# CHECK: cmplwi 0, 3, 128                # encoding: [0x28,0x03,0x00,0x80]
+         cmplwi 3, 128
 # CHECK: cmplw 2, 3, 4                   # encoding: [0x7d,0x03,0x20,0x40]
          cmplw 2, 3, 4
+# CHECK: cmplw 0, 3, 4                   # encoding: [0x7c,0x03,0x20,0x40]
+         cmplw 3, 4
 
 # FIXME: Trap mnemonics
 
Index: llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
===================================================================
--- llvm-head.orig/lib/Target/PowerPC/PPCInstrInfo.td
+++ llvm-head/lib/Target/PowerPC/PPCInstrInfo.td
@@ -2201,3 +2201,12 @@ defm : BranchExtendedMnemonic<"ne", 68>;
 defm : BranchExtendedMnemonic<"nu", 100>;
 defm : BranchExtendedMnemonic<"ns", 100>;
 
+def : InstAlias<"cmpwi $rA, $imm", (CMPWI CR0, gprc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpw $rA, $rB", (CMPW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmplwi $rA, $imm", (CMPLWI CR0, gprc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmplw $rA, $rB", (CMPLW CR0, gprc:$rA, gprc:$rB)>;
+def : InstAlias<"cmpdi $rA, $imm", (CMPDI CR0, g8rc:$rA, s16imm:$imm)>;
+def : InstAlias<"cmpd $rA, $rB", (CMPD CR0, g8rc:$rA, g8rc:$rB)>;
+def : InstAlias<"cmpldi $rA, $imm", (CMPLDI CR0, g8rc:$rA, u16imm:$imm)>;
+def : InstAlias<"cmpld $rA, $rB", (CMPLD CR0, g8rc:$rA, g8rc:$rB)>;
+


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184435 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 16:15:12 +00:00
Vladimir Medic
7231625f75 Optimize register parsing for MipsAsmParser. Allow symbolic aliases for FPU registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184411 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-20 11:21:49 +00:00
Bill Wendling
0c92f2a1c7 Don't pass in the TargetInstrInfo into the register info object. It doesn't use it. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184369 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:59:00 +00:00
David Blaikie
0159ae4295 DebugInfo: PR14763/r183329 correct the location of indirect parameters 
We had been papering over a problem with location info for non-trivial
types passed by value by emitting their type as references (this caused
the debugger to interpret the location information correctly, but broke
the type of the function). r183329 corrected the type information but
lead to the debugger interpreting the pointer parameter as the value -
the debug info describing the location needed an extra dereference.

Use a new flag in DIVariable to add the extra indirection (either by
promoting an existing DW_OP_reg (parameter passed in a register) to
DW_OP_breg + 0 or by adding DW_OP_deref to an existing DW_OP_breg + n
(parameter passed on the stack).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184368 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:55:13 +00:00
Bill Wendling
ba54bca472 Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184360 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:36:55 +00:00
Bill Wendling
f9fd58a44b Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184352 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 21:07:11 +00:00
Bill Wendling
ea44281d5d Access the TargetLoweringInfo from the TargetMachine object instead of caching it. The TLI may change between functions. No functionality change. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184349 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 20:51:24 +00:00
Matt Arsenault
ad966ea7a8 Move StructurizeCFG out of R600 to generic Transforms. 
Register it with PassManager

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184343 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 20:18:24 +00:00
Vladimir Medic
dd5fe2ffc6 The RenderMethod field in RegisterOperand class sets the name of the method on the target specific operand to call to add the target specific operand to an MCInst. This patch defines RenderMethod for mips RegisterOperand classes and removes redundant code from MipsAsmParser.cpp 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184292 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-19 10:14:36 +00:00
Matt Arsenault
70a3dc1bc2 Use GetUnderlyingObject instead of custom function 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184261 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 23:37:58 +00:00
Jim Grosbach
a95e3091eb ARM: Add optional datatype suffix to NEON mvn asm syntax. 
rdar://14194152

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184244 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 21:49:21 +00:00
Michael Gottesman
41502e1af7 [ARMTargetLowering] ARMISD::{SUB,ADD}{C,E} second result is a boolean implying that upper bits are always 0. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184231 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 20:49:45 +00:00
Michael Gottesman
8493edfb4b Converted an overly aggressive assert to a conditional check in AddCombineTo64bitMLAL. 
Said assert assumes that ADDC will always have a glue node as its second
argument and is checked before we even know that we are actually performing the
relevant MLAL optimization. This is incorrect since on ARM we *CAN* codegen ADDC
with a use list based second argument. Thus to have both effects, I converted
the assert to a conditional check which if it fails we do not perform the
optimization.

In terms of tests I can not produce an ADDC from the IR level until I get in my
multiprecision optimization patch which is forthcoming. The tests for said patch
would cause this assert to fail implying that said tests will provide the
relevant tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184230 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 20:49:40 +00:00
Nadav Rotem
ef2d9e3194 Fix 80 col violation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184228 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 20:41:52 +00:00
Kevin Enderby
bf811d602d Change the arm assembler to support this from the v7c spec: 
"When assembling to the ARM instruction set, the .N qualifier produces
an assembler error and the .W qualifier has no effect."

In the pre-matcher handler in the asm parser the ".w" (wide) qualifier 
when in ARM mode is now discarded. And an error message is now
produced when the ".n" (narrow) qualifier is used in ARM mode.

Test cases for these were added.

rdar://14064574


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184224 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 20:19:24 +00:00
Jack Carter
571dd98ea4 Mips ELF: Mark object file as ABI compliant 
When producing objects that are abi compliant we are 
marking neither the object file nor the assembly file
correctly and thus generate warnings. 

We need to set the EF_CPIC flag in the ELF header when
generating direct object.

Note that the warning is only generated when compiling without PIC.

When compiling with clang the warning will be suppressed by supplying:

 -Wa,-mno-shared -Wa,-call_nonpic

Also the following directive should also be added:

	.option	pic0

when compiling without PIC,  This eliminates the need for supplying:

  -mno-shared -call_nonpic

on the assembler command line.

Patch by Douglas Gilmore


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184220 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 19:47:15 +00:00
David Blaikie
13769fa725 Reduce indentation. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184213 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 18:03:17 +00:00
Stefanus Du Toit
23306deb92 Add support for encoding the HLE XACQUIRE and XRELEASE prefixes. 
For decoding, keep the current behavior of always decoding these as their REP
versions. In the future, this could be improved to recognize the cases where
these behave as XACQUIRE and XRELEASE and decode them as such.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184207 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 17:08:10 +00:00
Amaury de la Vieuville
beb920fce6 ARM: fix literal load with positive offset encoding 
When using a positive offset, literal loads where encoded
as if it was negative, because:
- The sign bit was not assigned to an operand
- The addrmode_imm12 operand was not encoding the sign bit correctly

This patch also makes the assembler look at the .w/.n specifier for
loads.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184182 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:13:05 +00:00
Amaury de la Vieuville
f8b60d6f30 ARM: add operands pre-writeback variants when needed 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184181 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:12:51 +00:00
Amaury de la Vieuville
ce046b98ed ARM: fix thumb literal loads decoding 
This fixes two previous issues:
- Negative offsets were not correctly disassembled
- The decoded opcodes were not the right one

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184180 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:03:06 +00:00
Amaury de la Vieuville
cea0032f73 ARM: thumb stores cannot use PC as dest register 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184179 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 08:02:56 +00:00
Bill Wendling
99cb622041 Use pointers to the MCAsmInfo and MCRegInfo. 
Someone may want to do something crazy, like replace these objects if they
change or something.

No functionality change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184175 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 07:20:20 +00:00
Bill Wendling
b44193dde1 Remove dead prototype. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184173 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-18 06:24:14 +00:00
Vincent Lejeune
f7c9b95f94 R600: PV stores Reg id, not index 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184117 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 20:16:40 +00:00
Vincent Lejeune
98f5cf8000 R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184116 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-17 20:16:26 +00:00
David Blaikie
0187e7a9ba DebugInfo: remove target-specific Frame Index handling for DBG_VALUE MachineInstrs 
Frame index handling is now target-agnostic, so delete the target hooks
for creation & asm printing of target-specific addressing in DBG_VALUEs
and any related functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184067 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-16 20:34:27 +00:00
David Blaikie
6d9dbd5526 Debug Info: Simplify Frame Index handling in DBG_VALUE Machine Instructions 
Rather than using the full power of target-specific addressing modes in
DBG_VALUEs with Frame Indicies, simply use Frame Index + Offset. This
reduces the complexity of debug info handling down to two
representations of values (reg+offset and frame index+offset) rather
than three or four.

Ideally we could ensure that frame indicies had been eliminated by the
time we reached an assembly or dwarf generation, but I haven't spent the
time to figure out where the FIs are leaking through into that & whether
there's a good place to convert them. Some FI+offset=>reg+offset
conversion is done (see PrologEpilogInserter, for example) which is
necessary for some SelectionDAG assumptions about registers, I believe,
but it might be possible to make this a more thorough conversion &
ensure there are no remaining FIs no matter how instruction selection
is performed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184066 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-16 20:34:15 +00:00
Andrew Trick
a3d82ce19f Support BufferSize on ProcResGroup for unified MOp schedulers. 
And add Sandybridge/Haswell resource buffers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184034 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:50:06 +00:00
Andrew Trick
a5ce5f36d3 Update machine models. Specify buffer sizes for OOO processors. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184033 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:50:02 +00:00
Andrew Trick
b86a0cdb67 Machine Model: Add MicroOpBufferSize and resource BufferSize. 
Replace the ill-defined MinLatency and ILPWindow properties with
with straightforward buffer sizes:
MCSchedMode::MicroOpBufferSize
MCProcResourceDesc::BufferSize

These can be used to more precisely model instruction execution if desired.

Disabled some misched tests temporarily. They'll be reenabled in a few commits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184032 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 04:49:57 +00:00
Tom Stellard
5aee09da12 R600: Add SI load support for v[24]i32 and store for v2i32 
Also add a seperate vector lit test file, since r600 doesn't seem to handle
v2i32 load/store yet, but we can test both for SI.

Patch by: Aaron Watry

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184021 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-15 00:09:31 +00:00
Tom Stellard
d6055262d2 R600: Use correct encoding for Vertex Fetch instructions on Cayman 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184016 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:30 +00:00
Tom Stellard
4efccd0fb1 R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman 
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184015 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:24 +00:00
Tom Stellard
c30b232349 R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184014 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:19 +00:00
Tom Stellard
2def95fc1e R600: Move instruction encoding definitions into a separate .td file 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184013 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 22:12:09 +00:00
Amaury de la Vieuville
a768a49548 ARM: fix thumb coprocessor instruction with pre-writeback disassembly 
was        stc2 p0, c0, [r0]!
instead of stc2 p0, c0, [r0,#0]!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183975 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 11:21:35 +00:00
Benjamin Kramer
d25ec760cb X86: cvtpi2ps is just an SSE instruction with MMX operands. It has no AVX equivalent. 
Give it the right register format so we can also emit it when AVX is enabled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183971 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 09:31:41 +00:00
JF Bastien
fe532ad6d6 Enable FastISel on ARM for Linux and NaCl, not MCJIT 
This is a resubmit of r182877, which was reverted because it broken
MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only
enabled for iOS. I've CC'ed people from the original review and revert.

FastISel was only enabled for iOS ARM and Thumb2, this patch enables it
for ARM (not Thumb2) on Linux and NaCl, but not MCJIT.

Thumb2 support needs a bit more work, mainly around register class
restrictions.

The patch punts to SelectionDAG when doing TLS relocation on non-Darwin
targets. I will fix this and other FastISel-to-SelectionDAG failures in
a separate patch.

The patch also forces FastISel to retain frame pointers: iOS always
keeps them for backtracking (so emitted code won't change because of
this), but Linux was getting much worse code that was incorrect when
using big frames (such as test-suite's lencod). I'll also fix this in a
later patch, it will probably require a peephole so that FastISel
doesn't rematerialize frame pointers back-to-back.

The test changes are straightforward, similar to:
  http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html
They also add a vararg test that got dropped in that change.

I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0
and all the tests pass. All the tests also pass on x86 make check-all. I
also re-ran the check-all tests that failed on ARM, and they all seem to
pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183966 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-14 02:49:43 +00:00
Tom Stellard
2948e693cb R600: Don't try to fix reg class when copying IMPLICIT_DEF to a register 
The test case for this is way too complex to be useful as a lit test,
and I was unable to reduce it.

https://bugs.freedesktop.org/show_bug.cgi?id=65438

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183937 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-13 20:14:00 +00:00
Benjamin Kramer
90cd06e90b Mips: Remove global set. 
Backends shouldn't retain any global state. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183927 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-13 19:06:52 +00:00
Amaury de la Vieuville
8117ac555d ARM: fix B decoding 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183914 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-13 16:41:55 +00:00
Amaury de la Vieuville
1290ce00a3 ARM: fix t2am_imm8_offset operand printing for imm=#-0 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183913 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-13 16:40:51 +00:00
Benjamin Kramer
19b30d56b2 X86: Make the cmov aliases work with intel syntax too. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183907 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-13 15:45:24 +00:00
David Blaikie
7e17024400 Revert r183854 (PPC: Fix switch warnings from r183841) 
Now that the PRED_BAD has been removed, this is failing the Clang
-Werror build due to -Wcovered-switch-default.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183863 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-12 20:57:32 +00:00
Bill Schmidt
6289533853 [PowerPC] Remove PRED_BAD from PPC::Predicate enumeration. 
I'm taking David Blaikie's suggestion to use an
Optional<PPC::Predicate> return value instead.  That's the right
solution for this problem.  Thanks for pointing out that possibility!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183858 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-12 20:22:24 +00:00
Bill Schmidt
dab366bf25 [PowerPC] Fix switch warnings from r183841. 
Introducing PRED_BAD caused some unexpected warnings that are now
suppressed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183854 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-12 19:20:32 +00:00
Bill Schmidt
d3f7766f23 [PowerPC] Expose some calling convention functions in PPCISelLowering.h. 
This is a preparatory patch for fast-isel support.  The instruction
selector will need to access some functions in PPCGenCallingConv.inc,
which in turn requires several helper functions to be defined.  These
are currently defined near the only use of PCCGenCallingConv.inc,
inside PPCISelLowering.cpp.  This patch moves the declaration of the
functions into the associated header file to provide the needed
visibility.

No functional change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183844 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-12 16:39:22 +00:00
Bill Schmidt
f69ead4651 Add artificial PRED_BAD to PPC::Predicate enumeration. 
Allows returning a PPC::Predicate from a function with a no-predicate
value possible.  Preparatory patch for fast-isel on PPC64 ELF.  No
behavioral change intended.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183841 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-12 15:14:42 +00:00
Ulrich Weigand
c1f4a4b264 [MC/DWARF] Support .debug_frame / .debug_line code alignment factors 
I've been comparing the object file output of LLVM's integrated
assembler against the external assembler on PowerPC, and one
area where differences still remain are in DWARF sections.

In particular, the GNU assembler generates .debug_frame and
.debug_line sections using a code alignment factor of 4, since
all PowerPC instructions have size 4 and must be aligned to a
multiple of 4.  However, current MC code hard-codes a code
alignment factor of 1.

This patch changes this by adding a "minimum instruction alignment"
data element to MCAsmInfo and using this as code alignment factor.

This requires passing a MCContext into MCDwarfLineAddr::Encode
and MCDwarfLineAddr::EncodeAdvanceLoc.  Note that one caller,
MCDwarfLineAddr::Write, didn't actually have that information
available.  However, it turns out that this routine is in fact
never used in the whole code base, so the patch simply removes
it.  If it turns out to be needed again at a later time, it
could be re-added with an updated interface.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183834 91177308-0d34-0410-b5e6-96231b3b80d8
 2013-06-12 14:46:54 +00:00