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Author SHA1 Message Date
Jakob Stoklund Olesen
19f5f71bba Revert "Use MachineInstr::readsWritesVirtualRegister to determine if a register is read." 
This reverts r104322. I think it was causing miscompilations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104323 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 17:36:32 +00:00
Jakob Stoklund Olesen
00c53caa33 Use MachineInstr::readsWritesVirtualRegister to determine if a register is read. 
This correctly handles partial redefines and undef uses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104322 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:42:30 +00:00
Jakob Stoklund Olesen
2afb7505c5 Teach VirtRegRewriter to handle spilling in instructions that have multiple 
definitions of the virtual register.

This happens when spilling the registers produced by REG_SEQUENCE:

%reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0

The rewriter would spill the register multiple times, dead store elimination
tried to keep up, but ended up cutting the branch it was sitting on.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104321 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:36:13 +00:00
Jakob Stoklund Olesen
63e6a488cb If the first definition of a virtual register is a partial redef, add an 
<imp-def> operand for the full register. This ensures that the full physical
register is marked live after register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104320 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 16:32:16 +00:00
Matt Fleming
d8a33ddcfe Currently, createMachOStreamer() is invoked directly in llvm-mc which 
isn't ideal if we want to be able to use another object file format.

Add a createObjectStreamer() factory method so that the correct object
file streamer can be instantiated for a given target triple.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104318 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 12:54:43 +00:00
Matt Fleming
7efaef6b82 Split out the x86_32 an x86_64 ELF backends as they handle ELF 
differently. This will make adding ELF support easier in the long run.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104317 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:39:07 +00:00
Matt Fleming
924c5e58f2 Add support for parsing the ELF .type assembler directive. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104316 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 11:36:59 +00:00
Lang Hames
24cdd2f82c Removed scaleNumbering method declaration from LiveInterval (not defined, not used). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104311 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 03:04:04 +00:00
Dale Johannesen
7d07b48b26 Fix i64->f64 conversion, x86-64, -no-sse. A bit 
tricky since there's a 3rd 64-bit type, MMX vectors.
PR 7135.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104308 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:52:33 +00:00
Evan Cheng
f7d87ee158 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104307 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:43:17 +00:00
Evan Cheng
b11ac950d6 Rename -pre-RA-sched=hybrid to -pre-RA-sched=list-hybrid. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104306 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:42:32 +00:00
Daniel Dunbar
596490682a Remove dead option. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104303 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:27:55 +00:00
Devang Patel
c0c5a26dea Simplify. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104302 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-21 00:10:20 +00:00
Daniel Dunbar
4ef6730632 Fix __crashreport_info__ declaration. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104300 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:50:19 +00:00
Evan Cheng
1cc3984148 Allow targets more controls on what nodes are scheduled by reg pressure, what for latency in hybrid mode. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104293 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 23:26:43 +00:00
Dan Gohman
0fe46d9b48 DominatorTree.getNode can return null for unreachable blocks. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104290 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 22:46:54 +00:00
Dan Gohman
9f383eb950 Minor code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104287 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 22:25:20 +00:00
Mikhail Glushenkov
dcc44670f4 Print a space after the colon. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104279 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 21:11:37 +00:00
Dan Gohman
a552878508 Make Solve check its own post-condition, to reduce clutter in the 
top-level LSRInstance logic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104278 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:59:23 +00:00
Dan Gohman
76c315a26c Add comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104276 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:52:00 +00:00
Daniel Dunbar
4e7f8390c0 MC/X86: Add movq alias for movabsq, to allow matching 64-bit immediates with movq. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104275 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:36:29 +00:00
Devang Patel
6ed0ce3240 Rename variable. add comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104274 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:35:24 +00:00
Dan Gohman
402d43529c More code cleanups. Use iterators instead of indices when indices 
aren't needed.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104273 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:33:18 +00:00
Daniel Dunbar
1fe591da3e X86: Model i64i32imm properly, as a subclass of all immediates. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104272 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:39 +00:00
Daniel Dunbar
0306e3ddbf X86: Fix immediate type of FOO64i32 operations. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104271 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:35 +00:00
Daniel Dunbar
4072886a69 tblgen/Target: Add a isAsmParserOnly bit, and teach the disassembler to honor 
it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104270 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:20:32 +00:00
Dan Gohman
c6519f916b Fix OptimizeShadowIV to set Changed. Change OptimizeLoopTermCond to set 
Changed directly instead of using a return value.

Rename FilterOutUndesirableDedicatedRegisters's Changed variable to
distinguish it from LSRInstance's Changed member.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104269 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:05:31 +00:00
Dan Gohman
f7ff37d674 Add some comments. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104268 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:00:41 +00:00
Dan Gohman
d974a0e9d6 Simplify this code. Don't do a DomTreeNode lookup for each visited block. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104267 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 20:00:25 +00:00
Devang Patel
ee43286ca9 Refactor. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104265 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:57:06 +00:00
Matt Fleming
ab3b3651ad Grammar fix. This is a test commit. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104264 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:45:09 +00:00
Dan Gohman
ea507f5c28 Minor code cleanups. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104263 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:44:23 +00:00
Dan Gohman
f182b23f8f When canonicalizing icmp operand order to put the loop invariant 
operand on the left, the interesting operand is on the right. This
fixes a bug where LSR was failing to recognize ICmpZero uses,
which led it to be unable to reverse the induction variable in the
attached testcase.

Delete test/CodeGen/X86/stack-color-with-reg-2.ll, because its test
is extremely fragile and hard to meaningfully update.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104262 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:26:52 +00:00
Mikhail Glushenkov
eb0971529d llvmc: Make segfault detection work on Win32. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104261 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:23:47 +00:00
Dan Gohman
9da1bf4845 Set Changed to true when canonicalizing ICmp operand order; even though 
it isn't a very interesting change, it's a change nonetheless.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104260 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 19:16:03 +00:00
Bob Wilson
63b8845e78 Handle Neon v2f64 and v2i64 vector shuffles as register copies. 
This fixes the remaining issue with pr7167.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104257 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:39:53 +00:00
Jim Grosbach
76526f8863 Remove dbg_value workaround and associated command line option 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104254 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:34:01 +00:00
Dan Gohman
53e184980d Delete MMX_MOVQ64gmr. It was the same as MMX_MOVQ64mr, but it didn't 
have a pattern and it had an invalid encoding.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104244 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 18:05:01 +00:00
Dale Johannesen
5f07d5224d The PPC MFCR instruction implicitly uses all 8 of the CR 
registers.  Currently it is not so marked, which leads to
VCMPEQ instructions that feed into it getting deleted.
If it is so marked, local RA complains about this sequence:
 vreg = MCRF  CR0
 MFCR  <kill of whatever preg got assigned to vreg>
All current uses of this instruction are only interested in
one of the 8 CR registers, so redefine MFCR to be a normal
unary instruction with a CR input (which is emitted only as
a comment).  That avoids all problems.  7739628.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104238 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 17:48:26 +00:00
Devang Patel
69b4d1caff Strip llvm.dbg.lv also. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104236 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:49:22 +00:00
Dan Gohman
24a7c30822 Rename a variable to avoid shadowing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104234 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:41:11 +00:00
Devang Patel
26c1e56f13 Split DbgVariable. Eventually, variable info will be communicated through frame index, or DBG_VALUE instruction, or collection of DBG_VALUE instructions. Plus each DbgVariable may not need a label. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104233 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:36:41 +00:00
Dan Gohman
4766744072 Minor code simplification. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104232 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:23:28 +00:00
Dan Gohman
e5e4ff974d Fix assembly parsing and encoding of the pushf and popf family of 
instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104231 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 16:16:00 +00:00
Dan Gohman
100804f494 Set neverHasSideEffects on 64-bit pushf and popf, for consistency with 
16-bit and 32-bit pushf and popf.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104228 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 15:42:55 +00:00
Dan Gohman
5ce6d05ad6 Move the code for deleting BaseRegs and LSRUses into helper functions, 
and fix a bug that valgrind noticed where the code would std::swap an
element with itself.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104225 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 15:17:54 +00:00
Benjamin Kramer
c37791e875 Reduce string trashing. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104223 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 14:14:22 +00:00
Evan Cheng
15a16def6e Add a hybrid bottom up scheduler that reduce register usage while avoiding 
pipeline stall. It's useful for targets like ARM cortex-a8. NEON has a lot
of long latency instructions so a strict register pressure reduction
scheduler does not work well.
Early experiments show this speeds up some NEON loops by over 30%.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104216 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 06:13:19 +00:00
Nick Lewycky
761fd4c1d9 Fix typo in comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104209 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 03:30:09 +00:00
Dan Gohman
14aaeac5cf Define the x86 pause instruction. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104204 91177308-0d34-0410-b5e6-96231b3b80d8
 2010-05-20 01:35:50 +00:00