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Commit Graph

10078 Commits

Author SHA1 Message Date
Dan Gohman
1e3121c80a Include the use kind along with the expression in the key of the
use sharing map. The reconcileNewOffset logic already forces a
separate use if the kinds differ, so incorporating the kind in the
key means we can track more sharing opportunities.

More sharing means fewer total uses to track, which means smaller
problem sizes, which means the conservative throttles don't kick
in as often.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106396 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 21:29:59 +00:00
Dan Gohman
b92654d9c9 Fix ScalarEvolution's "exhaustive" trip count evaluation code to avoid
assuming that loops are in canonical form, as ScalarEvolution doesn't
depend on LoopSimplify itself. Also, with indirectbr not all loops can
be simplified. This fixes PR7416.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106389 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 14:17:24 +00:00
Bruno Cardoso Lopes
f4f4bad696 Refactor aliased packed logical instructions, also add
AVX AND,OR,XOR,NAND{P}{S,D}{rr,rm} instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106374 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 02:44:01 +00:00
Evan Cheng
0110ac66eb Disable sibcall optimization for Thumb1 for now since Thumb1RegisterInfo::emitEpilogue is not expecting them.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106368 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 01:01:32 +00:00
Bruno Cardoso Lopes
be4d595afd Shrink down code and add for free AVX {MIN,MAX}P{S,D}{rm,rr} instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106366 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:37:31 +00:00
Chris Lattner
1cf44fc051 fix rdar://7873482 by teaching the instruction encoder to emit
segment prefixes.  Daniel wrote most of this patch.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106364 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-19 00:34:00 +00:00
Evan Cheng
96c3da6436 Move ARM if-conversion before post-ra scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106355 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:32:07 +00:00
Evan Cheng
86050dc8cc Allow ARM if-converter to be run after post allocation scheduling.
- This fixed a number of bugs in if-converter, tail merging, and post-allocation
  scheduler. If-converter now runs branch folding / tail merging first to
  maximize if-conversion opportunities.
- Also changed the t2IT instruction slightly. It now defines the ITSTATE
  register which is read by instructions in the IT block.
- Added Thumb2 specific hazard recognizer to ensure the scheduler doesn't
  change the instruction ordering in the IT block (since IT mask has been
  finalized). It also ensures no other instructions can be scheduled between
  instructions in the IT block.

This is not yet enabled.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106344 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 23:09:54 +00:00
Jakob Stoklund Olesen
0465bcffbb TwoAddressInstructionPass::CoalesceExtSubRegs can insert INSERT_SUBREG
instructions, but it doesn't really understand live ranges, so the first
INSERT_SUBREG uses an implicitly defined register.

Fix it in LiveVariableAnalysis by adding the <undef> flag.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106333 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:29:44 +00:00
Evan Cheng
6a5e2832d0 Fix an inverted condition.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106330 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 22:17:13 +00:00
Jakob Stoklund Olesen
52c61ec164 When using ADDri to get the address of a stack object, 255 is a conservative
limit on the offset that can be materialized without using the register
scavenger.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106312 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 20:59:25 +00:00
Dan Gohman
3bf63768e5 Revert r106304 (105548 and friends), which are the SCEVComplexityCompare
optimizations. There is still some nondeterminism remaining.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106306 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:54:20 +00:00
Bruno Cardoso Lopes
6e0a99a7ab Teach tablegen how to inherit from classes in 'defm' definitions.
The rule is simple: only inherit from a class list if they come
in the end, after the last multiclass.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106305 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:53:41 +00:00
Dan Gohman
78db186d2d Reapply 105540, 105542, and 105548, and revert r105732.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106304 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:26:04 +00:00
Dale Johannesen
c66cdf74a9 Enable tail calls on ARM by default, with some
basic tests.

This has been well tested on Darwin but not elsewhere.
It should work provided the linker correctly resolves
  B.W  <label in other function>
which it has not seen before, at least from llvm-based
compilers.  I'm leaving the arm-tail-calls switch in
until I see if there's any problems because of that;
it might need to be disabled for some environments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106299 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 19:00:18 +00:00
Jakob Stoklund Olesen
0d8ba3303b Treat the ARM inline asm {cc} constraint as a physreg (%CPSR), just like X86
does for {flags}. If we create virtual registers of the CCR class, RegAllocFast
may try to spill them, and we can't do that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106289 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 16:49:33 +00:00
Dan Gohman
c185a12f25 Don't write a file named "&1".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106269 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:49:17 +00:00
Dan Gohman
a52838285b Disable indvars on loops when LoopSimplify form is not available.
This fixes PR7333.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106267 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:35:11 +00:00
Dan Gohman
e54081088e Don't maintain a set of deleted nodes; instead, use a HandleSDNode
to track a node over CSE events. This fixes PR7368.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106266 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:24:29 +00:00
Bruno Cardoso Lopes
d7f9cc4de7 Add {mix,max}{ss,sd}{rr,rm} AVX forms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106264 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:12:56 +00:00
Dan Gohman
8a7f7426ee Fold the ShrinkDemandedOps pass into the regular DAGCombiner pass,
which is faster, simpler, and less surprising.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106263 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 01:05:21 +00:00
Dan Gohman
0a13b89b24 Make this test less fragile.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106255 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-18 00:06:03 +00:00
Dale Johannesen
218883aa70 Testcase for llvm-gcc 106225.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106226 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 17:43:14 +00:00
Rafael Espindola
1e81966626 Remove arm_apcscc from the test files. It is the default and doing this
matches what llvm-gcc and clang now produce.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106221 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 15:18:27 +00:00
Bruno Cardoso Lopes
eba8f1893b For a tablegen expression such as !if(a,b,c), let 'a'
be evaluated for 'bit' operators


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106185 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-17 00:31:36 +00:00
Bruno Cardoso Lopes
e87de41189 let the '!eq' expression support 'int' and 'bit' types
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106171 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 23:24:12 +00:00
Jakob Stoklund Olesen
c66d0f2a93 Allow a register to be redefined multiple times in a basic block.
LiveVariableAnalysis was a bit picky about a register only being redefined once,
but that really isn't necessary.

Here is an example of chained INSERT_SUBREGs that we can handle now:

68      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1028<kill>, 14
                register: %reg1040 +[70,134:0)
76      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1029<kill>, 13
                register: %reg1040 replace range with [70,78:1) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,134:0)  0@78-(134) 1@70-(78)
84      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1030<kill>, 12
                register: %reg1040 replace range with [78,86:2) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,134:0)  0@86-(134) 1@70-(78) 2@78-(86)
92      %reg1040<def> = INSERT_SUBREG %reg1040, %reg1031<kill>, 11
                register: %reg1040 replace range with [86,94:3) RESULT: %reg1040,0.000000e+00 = [70,78:1)[78,86:2)[86,94:3)[94,134:0)  0@94-(134) 1@70-(78) 2@78-(86) 3@86-(94)

rdar://problem/8096390

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106152 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:29:40 +00:00
Jim Grosbach
d7d4ce3c9b modify so the test doesn't drop an output file in the test source directory.
The test should also likely have some FileCheck bits to validate the
output(?).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106146 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 21:07:06 +00:00
Devang Patel
4c47095665 Be specific. Use FileCheck.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106135 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 19:39:45 +00:00
Rafael Espindola
e96af56a5b Make sure that simplify libcalls does not replace a call with one calling
convention with a new call with a different calling convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106134 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 19:34:01 +00:00
Devang Patel
0f800a6eb8 This requires more investigation. Unblock buildbots for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106122 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 18:19:49 +00:00
Devang Patel
6e67c6cb3c Update test to explicitly capture llc output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106121 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 18:04:12 +00:00
Benjamin Kramer
ea9ca0236d simplify-libcalls: fold strncmp(x, y, 1) -> memcmp(x, y, 1)
The memcmp will be optimized further and even the pathological case
'strstr(x, "x") == x' generates optimal code now.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106097 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 10:30:29 +00:00
Evan Cheng
46df4eb46e Make post-ra scheduling, anti-dep breaking, and register scavenger (conservatively) aware of predicated instructions. This enables ARM to move if-conversion before post-ra scheduler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106091 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-16 07:35:02 +00:00
Bill Wendling
d361a77f14 Create a more targeted fix for not sinking instructions into a range where it
will conflict with another live range. The place which creates this scenerio is
the code in X86 that lowers a select instruction by splitting the MBBs. This
eliminates the need to check from the bottom up in an MBB for live pregs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106066 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 23:46:31 +00:00
Rafael Espindola
5869dc005e Update test to match recent llvm-gcc change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106056 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 22:16:40 +00:00
Jakob Stoklund Olesen
8a3eab9b20 Remove the local register allocator.
Please use the fast allocator instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106051 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 21:58:33 +00:00
Benjamin Kramer
386e918438 simplify-libcalls: fold strstr(a, b) == a -> strncmp(a, b, strlen(b)) == 0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106047 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 21:34:25 +00:00
Rafael Espindola
2bbaf4d06e Set the mtriple in some tests so that they use AAPCS.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106041 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 20:42:00 +00:00
Mon P Wang
9c4a84b4f3 Fixed vector widening of binary instructions that can trap. Patch by Visa Putkinen!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106038 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 20:29:05 +00:00
Chris Lattner
868ee9460c fix fastisel to handle GS and FS relative pointers. Patch by
Nelson Elhage!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106031 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:08:40 +00:00
Rafael Espindola
2ebb4f81f7 Remove the arm_aapcscc marker from the tests. It is the default
for the linux targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@106029 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 19:04:29 +00:00
Jakob Stoklund Olesen
75ac4d9c2d Avoid processing early clobbers twice in RegAllocFast.
Early clobbers defining a virtual register were first alocated to a physreg and
then processed as a physreg EC, spilling the virtreg.

This fixes PR7382.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105998 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 16:20:57 +00:00
Jakob Stoklund Olesen
40d07bbebb Add CoalescerPair helper class.
Given a copy instruction, CoalescerPair can determine which registers to
coalesce in order to eliminate the copy. It deals with all the subreg fun to
determine a tuple (DstReg, SrcReg, SubIdx) such that:

- SrcReg is a virtual register that will disappear after coalescing.
- DstReg is a virtual or physical register whose live range will be extended.
- SubIdx is 0 when DstReg is a physical register.
- SrcReg can be joined with DstReg:SubIdx.

CoalescerPair::isCoalescable() determines if another copy instruction is
compatible with the same tuple. This fixes some NEON miscompilations where
shuffles are getting coalesced as if they were copies.

The CoalescerPair class will replace a lot of the spaghetti logic in JoinCopy
later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105997 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 16:04:21 +00:00
Bob Wilson
852a7e362e Generalize the pre-coalescing of extract_subregs feeding reg_sequences,
replacing the overly conservative checks that I had introduced recently to
deal with correctness issues.  This makes a pretty noticable difference
in our testcases where reg_sequences are used.  I've updated one test to
check that we no longer emit the unnecessary subreg moves.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105991 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-15 05:56:31 +00:00
Chris Lattner
ea3447ac76 apparently lots of dupes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105956 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 20:19:03 +00:00
Chris Lattner
6b601536ff fix a nasty bug where we were not treating available_externally
symbols as declarations in the X86 backend.  This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:

symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression

This fixes PR7353.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 20:11:56 +00:00
Chris Lattner
82c4fbbc2f remove old test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105953 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 20:07:43 +00:00
Chris Lattner
efaadb6171 rename test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105952 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 20:07:34 +00:00
Chris Lattner
e58867e55e jump threading can't split a critical edge from an indirectbr. This
fixes PR7356.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105950 91177308-0d34-0410-b5e6-96231b3b80d8
2010-06-14 19:45:43 +00:00