135568 Commits

Author SHA1 Message Date
Geoff Berry
265e1496c0 [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pass. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276193 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:45:58 +00:00
Adam Nemet
957976efe6 [OptDiag,LV] Add hotness attribute to analysis remarks
The earlier change added hotness attribute to missed-optimization
remarks.  This follows up with the analysis remarks (the ones explaining
the reason for the missed optimization).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276192 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:44:26 +00:00
Adam Nemet
ef4767cee4 [OptDiag] Take the IR Value as a const pointer
This helps because LoopAccessReport is passed around as a const
reference and we derive the basic block passed as the Value parameter
from the instruction in LoopAccessReport.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276191 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:44:22 +00:00
Adam Nemet
9ce2fff872 [OptDiag] Wrap a long line
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276190 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:44:18 +00:00
Artem Belevich
5001c928a7 [NVPTX] Renamed NVPTXLowerKernelArgs -> NVPTXLowerArgs. NFC.
After r276153 the pass applies to both kernels and regular functions.

Differential Revision: https://reviews.llvm.org/D22583

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276189 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:44:07 +00:00
Xinliang David Li
d05d2538c7 [Profile] support directory reading in profile merging
Differential Revision:  http://reviews.llvm.org/D22560




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276185 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:31:29 +00:00
Tim Northover
6f08925c54 GlobalISel: implement Legalization querying framework.
This adds an (incomplete, inefficient) framework for deciding what to do with
some operation on a given type.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276184 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:13:29 +00:00
Ahmed Bougacha
518182510a [AArch64][FastISel] Select -O0 legal cmpxchg.
At -O0, cmpxchg survives AtomicExpand: it's mostly straightforward
to select it in fast-isel, and let the pseudo be expanded later.

extractvalues on the result are the tricky part: the generic logic
only works for legal types (and it would be painful to make it
support illegal types), so we can only support i32/i64 cmpxchg.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276183 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:12:32 +00:00
Ahmed Bougacha
e212aa990b [AArch64][FastISel] Select atomic stores into STLR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276182 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:12:27 +00:00
David Majnemer
991d814755 [GVNHoist] Don't hoist PHI nodes
We hoisted PHIs without respecting their special insertion point in the
block, leading to verfier errors.

This fixes PR28626.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276181 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 21:05:01 +00:00
Davide Italiano
c2a8447473 [SCCP] Zap multiple return values.
We can replace the return values with undef if we replaced all
the call uses with a constant/undef.

Differential Revision:  https://reviews.llvm.org/D22336

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276174 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 20:17:13 +00:00
Justin Lebar
0cd5bfadb9 [LSV] Don't move stores across may-load instrs, and loosen restrictions on moving loads.
Summary:
Previously we wouldn't move loads/stores across instructions that had
side-effects, where that was defined as may-write or may-throw.  But
this is not sufficiently restrictive: Stores can't safely be moved
across instructions that may load.

This patch also adds a DEBUG check that all instructions in our chain
are either loads or stores.

Reviewers: asbirlea

Subscribers: llvm-commits, jholewinski, arsenm, mzolotukhin

Differential Revision: https://reviews.llvm.org/D22547

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276171 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 20:07:37 +00:00
Justin Lebar
05fc242425 [LSV] Vectorize up to side-effecting instructions.
Summary:
Previously if we had a chain that contained a side-effecting
instruction, we wouldn't vectorize it at all.  Now we'll vectorize
everything that comes before the side-effecting instruction.

Reviewers: asbirlea

Subscribers: arsenm, jholewinski, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D22536

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276170 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 20:07:34 +00:00
George Burgess IV
bd986a7d74 [MSSA] Add an overload for getClobberingMemoryAccess.
A seemingly common use for the walker's getClobberingMemoryAccess
function is:

```
MemoryAccess *getClobber(MemorySSAWalker *W, MemoryUseOrDef *MUD) {
  const Instruction *I = MUD->getMemoryInst();
  return W->getClobberingMemoryAccess(I);
}
```

Which is kind of redundant, since walkers will ultimately query MSSA to
find out which MemoryAccess `I` maps to (...which is always `MUD`).

So, this patch adds an overload of getClobberingMemoryAccess that
accepts MemoryAccesses directly. As a result, the Instruction overload
of getClobberingMemoryAccess becomes a lightweight wrapper around our
new overload.

Additionally, this patch un`virtual`izes the Instruction overload of
getClobberingMemoryAccess, since there doesn't seem to be a walker that
benefits from that being virtual, and I can't think of how else one
would implement it. Happy to make it virtual again if we would benefit
from doing so.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276169 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 19:51:34 +00:00
Rui Ueyama
e30c989e49 [pdbdump] Use the "flow" style to print out a sequence of uint32_t.
Summary: Lists can be written either with "-" or "[]" in YAML.

Differential Revision: https://reviews.llvm.org/D22579

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276168 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 19:41:47 +00:00
Tim Northover
6d11357f4b GlobalISel: properly conditionalize LLT use.
We can't guard the include of LowLevelType.h because getType and setType are
(trivial) functions even when GlobalISel isn't built.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276160 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 19:17:29 +00:00
Tim Northover
4951996d06 GlobalISel: implement low-level type with just size & vector lanes.
This should be all the low-level instruction selection needs to determine how
to implement an operation, with the remaining context taken from the opcode
(e.g. G_ADD vs G_FADD) or other flags not based on type (e.g. fast-math).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276158 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 19:09:30 +00:00
Alina Sbirlea
c5f802f164 Properly ifdef the use of cpuid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276156 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 18:54:26 +00:00
Artem Belevich
6de1b85db3 [NVPTX] deal with all aggregate return types.
Fixes a crash in llvm_unreachable when a function has array return type.

Differential Revision: https://reviews.llvm.org/D22524

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276154 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 18:39:52 +00:00
Artem Belevich
86d9bce726 [NVPTX] Improve lowering of byval args of device functions.
Avoid unnecessary spills of byval arguments of device functions to
local space on SASS level and subsequent pointer conversion to generic
address space that follows. Instead, make a local copy in IR, provide
a way to access arguments directly, and let LLVM optimize the copy away
when possible.

Differential Review: https://reviews.llvm.org/D21421

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276153 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 18:39:47 +00:00
Adam Nemet
5f9c124059 [OptDiag] Fix function comment
Function is not passed unlike in the original of this
(llvm::emitOptimizationRemarkMissed).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276150 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 18:16:45 +00:00
Alina Sbirlea
e422546afb [cpu-detection] Cleanup of Host.cpp.
Summary:
Mirroring most cleanup changed from compiler-rt/lib/builtins/cpu_model.
x86 methods are still returning a bool.

Reviewers: llvm-commits, echristo, craig.topper, sanjoy

Subscribers: mehdi_amini

Differential Revision: https://reviews.llvm.org/D22480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276149 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 18:15:29 +00:00
Sanjay Patel
e4f2c83149 minimize tests and auto-generate checks
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276147 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 17:58:20 +00:00
Sanjay Patel
402ec84aa3 move decomposeBitTestICmp() to Transforms/Utils; NFC
As noted in https://reviews.llvm.org/D22537 , we can use this functionality in 
visitSelectInstWithICmp() and InstSimplify, but currently we have duplicated
code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276140 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 17:18:45 +00:00
Wei Mi
edd8aa084e Fix test/Analysis/ScalarEvolution/scev-expander-existing-value-offset.ll for rL276136.
The content in this testcase was accidentally duplicated. Fix the error.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276139 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 16:54:58 +00:00
Wei Mi
fe11fa4d16 Use ValueOffsetPair to enhance value reuse during SCEV expansion.
In D12090, the ExprValueMap was added to reuse existing value during SCEV expansion.
However, const folding and sext/zext distribution can make the reuse still difficult.

A simplified case is: suppose we know S1 expands to V1 in ExprValueMap, and
  S1 = S2 + C_a
  S3 = S2 + C_b
where C_a and C_b are different SCEVConstants. Then we'd like to expand S3 as
V1 - C_a + C_b instead of expanding S2 literally. It is helpful when S2 is a
complex SCEV expr and S2 has no entry in ExprValueMap, which is usually caused
by the fact that S3 is generated from S1 after const folding.

In order to do that, we represent ExprValueMap as a mapping from SCEV to
ValueOffsetPair. We will save both S1->{V1, 0} and S2->{V1, C_a} into the
ExprValueMap when we create SCEV for V1. When S3 is expanded, it will first
expand S2 to V1 - C_a because of S2->{V1, C_a} in the map, then expand S3 to
V1 - C_a + C_b.

Differential Revision: https://reviews.llvm.org/D21313


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276136 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 16:40:33 +00:00
Sanjay Patel
475ddcccb2 fix documentation comments; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276135 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 16:30:55 +00:00
Matt Arsenault
20e6e25350 AMDGPU: Add missing test coverage for control flow breaks
None of the current lit tests hit si_break handling.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276129 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 15:20:35 +00:00
Yaxun Liu
59e8cabf31 AMDGPU: Fix bug causing crash due to invalid opencl version metadata.
Differential Revision: https://reviews.llvm.org/D22526

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276119 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 14:38:06 +00:00
Renato Golin
88ea57fa26 [docs] Fixing Sphinx warnings to unclog the buildbot
Lots of blocks had "llvm" or "nasm" syntax types but either weren't following
the syntax, or the syntax has changed (and sphinx hasn't keep up) or the type
doesn't even exist (nasm?).

Other documents had :options: what were invalid. I only removed those that had
warnings, and left the ones that didn't, in order to follow the principle of
least surprise.

This is like this for ages, but the buildbot is now failing on errors. It may
take a while to upgrade the buildbot's sphinx, if that's even possible, but
that shouldn't stop us from getting docs updates (which seem down for quite
a while).

Also, we're not losing any syntax highlight, since when it doesn't parse, it
doesn't colour. Ie. those blocks are not being highlighted anyway.

I'm trying to get all docs in one go, so that it's easy to revert later if we
do fix, or at least easy to know what's to fix.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276109 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 12:16:38 +00:00
Benjamin Kramer
3ac7591eee Revert "[InstCombine] Enable cast-folding in logic(cast(icmp), cast(icmp))"
Makes InstCombine infloop when compiling v8.

This reverts commit r275989 and r276105.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276106 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 11:40:16 +00:00
Tobias Grosser
90e252f6f7 [InstCombine] Provide more test cases for cast-folding [NFC]
Summary: In r275989 we enabled the folding of `logic(cast(icmp), cast(icmp))` to `cast(logic(icmp, icmp))`. Here we add more test cases to assure this folding works for all logical operations `and`/`or`/`xor`.

Reviewers: grosser

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22561

Contributed-by: Matthias Reisinger

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276105 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 11:24:27 +00:00
Simon Pilgrim
002e4b5635 [X86][SSE] Add cost model values for CTPOP of vectors
This patch adds costs for the vectorized implementations of CTPOP, the default values were seriously underestimating the cost of these and was encouraging vectorization on targets where serialized use of POPCNT would be much better.

Differential Revision: https://reviews.llvm.org/D22456

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276104 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 10:41:28 +00:00
Diana Picus
ab726d976d [ARM] Skip inline asm memory operands in DAGToDAGISel
Retry r275776 (no changes, we suspect the issue was with another commit).

The current logic for handling inline asm operands in DAGToDAGISel interprets
the operands by looking for constants, which should represent the flags
describing the kind of operand we're dealing with (immediate, memory, register
def etc). The operands representing actual data are skipped only if they are
non-const, with the exception of immediate operands which are skipped explicitly
when a flag describing an immediate is found.

The oversight is that memory operands may be const too (e.g. for device drivers
reading a fixed address), so we should explicitly skip the operand following a
flag describing a memory operand. If we don't, we risk interpreting that
constant as a flag, which is definitely not intended.

Fixes PR26038

Differential Revision: https://reviews.llvm.org/D22103

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276101 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 09:48:24 +00:00
Renato Golin
f12c36b2bc [docs] fix cmake code-block warning
This will unblock the llvm-sphinx-buildbot, which is currently failing due
to a warning being treated as error.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276100 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 09:47:09 +00:00
Renato Golin
0aa76a9edf [docs] Add proposals to index file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276099 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 09:38:04 +00:00
Renato Golin
69d7e1c385 [docs] GitHub Proposal for LLVM
This document was crafted from the various (320+) emails between 2nd June and
20th July regarding the move to GitHub. It tried to consolidate every issue that
was raised and every solution that was presented to have a GitHub repository
with sub-modules.

It *does not* try to argue whether sub-modules are better or worse than any other
Git solution, nor if Git is better than any other VCS, nor if GitHub is better
than any other free code hosting service. This is just the final conclusions of
48 days and 320 emails (plus a lot of IRC discussions) on the LLVM community.

This document will be presented at the survey that the foundation will setup for
us to decide if we move to this solution or not. It reflects what was discussed
on the lists, but it's not authoritative. If something is not clear enough,
please refer to the mailing list discussions (hint: search for "GitHub").

Review: https://reviews.llvm.org/D22463

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276097 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 09:09:58 +00:00
Craig Topper
69842b3053 [AVX512] Add a missing NoVLX to give priority to the AVX512 version of the pattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276088 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 05:05:50 +00:00
Craig Topper
c269039612 [X86] Use 'HasAVX1Only' to properly give priority to the AVX2 version without relying on file ordering.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276087 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 05:05:48 +00:00
Craig Topper
b83989e3bb [X86] Create some multiclasses to reduce the repeated patterns for VEXTRACT(F/I)128/VINSERT(I/F)128. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276086 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 05:05:46 +00:00
Craig Topper
f5da1386b2 [X86] Create some wrapper multiclasses to create AVX and SSE shift instructions with less repeated code. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276085 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 05:05:44 +00:00
David Majnemer
476169b208 Forgot to add a test for r276008.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276082 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 04:13:05 +00:00
David Majnemer
9c5be7601f Revert "Disable this-return argument forwarding on ARM/AArch64"
Inference of the 'returned' attribute was fixed in r276008, lets try
turning the backend support back on.

This reverts commit r275677.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276081 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 04:13:01 +00:00
Adam Nemet
dc062efb06 [LV] Add hotness attribute to missed-optimization remarks
The new OptimizationRemarkEmitter analysis pass is hooked up to both new
and old PM passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276080 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 04:03:43 +00:00
Michael Zolotukhin
11bf1ab282 Revert "Revert r275883 and r275891. They seem to cause PR28608."
This reverts commit r276064, and thus reapplies r275891 and r275883 with
a fix for PR28608.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276077 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 01:55:27 +00:00
Saleem Abdulrasool
ddff6280e7 llvm-readobj: add some more aliases
Alias -d and -t from readelf in llvm-readobj which effectively replaces the
tool.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276075 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 01:16:28 +00:00
Justin Lebar
dbf6ad39ae [LSV] Don't assume that loads/stores appear in address order in the BB.
Summary:
getVectorizablePrefix previously didn't work properly in the face of
aliasing loads/stores.  It unwittingly assumed that the loads/stores
appeared in the BB in address order.  If they didn't, it would do the
wrong thing.

Reviewers: asbirlea, tstellarAMD

Subscribers: arsenm, llvm-commits, mzolotukhin

Differential Revision: https://reviews.llvm.org/D22535

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276072 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 00:55:12 +00:00
Yunzhong Gao
30f6cf738e Fixing a few places in this doc which look like obvious typos.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276070 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 00:40:54 +00:00
Matthias Braun
e3d8cd87b2 Revert "RegScavenging: Add scavengeRegisterBackwards()"
Reverting this commit for now as it seems to be causing failures on
test-suite tests on the clang-ppc64le-linux-lnt bot.

This reverts commit r276044.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276068 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 00:21:32 +00:00
Kyle Butt
3d7281b8c9 Codegen: Tail Duplication: Only duplicate into layout pred if it is a CFG Pred.
Add a check that the layout predecessor of a block is an actual CFG
predecssor of the block as well. No current code fails this check, but
upcoming patches can trigger this, and it makes sense to separate it
out.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276066 91177308-0d34-0410-b5e6-96231b3b80d8
2016-07-20 00:01:51 +00:00