136147 Commits

Author SHA1 Message Date
Ivan Krasin
2cc035abb5 Add -lowertypetests-bitsets-level to control bitsets generation.
Summary:
Sometimes, bitsets could get really large (>300k entries) and
we might want to drop a check, as it would have a too much cost.

Adding a flag to control how much penalty are we willing to pay
for bitsets.

Reviewers: kcc

Differential Revision: https://reviews.llvm.org/D23088

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277556 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-03 00:59:38 +00:00
Sanjay Patel
1e0bd5f23c add vector test for icmp+sub
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277555 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-03 00:36:54 +00:00
Daniel Berlin
9d6e4f22e7 Support for lifetime begin/end markers in the MemorySSA use optimizer
Summary: Depends on D23072

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23076

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277553 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-03 00:01:46 +00:00
Matthias Braun
b1f5b4a5bd CommandFlags.h/llc: Move StopAfter/StartBefore options to llc.
Move those two options to llc:

The options in CommandFlags.h are shared by dsymutil, gold, llc,
llvm-dwp, llvm-lto, llvm-mc, lto, opt.

-stop-after/-start-after only affect codegen passes however only gold and llc
actually create codegen passes and I believe these flags to be only
useful for users of llc. For the other tools they are just highly
confusing: -stop-after claims to "Stop compilation after a specific
pass" which is not true in the context of the "opt" tool.

Differential Revision: https://reviews.llvm.org/D23050

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277551 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:36:06 +00:00
Sanjoy Das
f9a50810e2 [Verifier] Add more tests related to non-integral pointers
As suggested by Matt Arsenault in post-commit review.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277550 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:32:53 +00:00
Derek Schuff
d8ef8b0e48 [WebAssembly] Remove unnecessary subtarget checks in peephole pass
Leftover from D22686; the passes can handle all the instructions
unconditionally; only isel needs to care whether to generate them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277549 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:31:56 +00:00
Rui Ueyama
ffc05ed951 Fix a test for r277545.
This change should have been submitted with that commit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277548 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:25:59 +00:00
Rui Ueyama
09f1981bfa pdbdump: Do not treat stream 0 pages as allocated pages.
I examined a few PDBs and all of them treated pages for stream 0
are unused, thus they were unmarked in their free page bitmap.
I think we should do the same thing for compatibility.

Differential Revision: https://reviews.llvm.org/D23047

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277545 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:22:46 +00:00
Evgeniy Stepanov
66c2ec1bb4 [safestack] Layout large allocas first to reduce fragmentation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277544 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:21:30 +00:00
Derek Schuff
75834f76b2 [WebAssembly] Initial SIMD128 support.
Kicks off the implementation of wasm SIMD128 support (spec:
https://github.com/stoklund/portable-simd/blob/master/portable-simd.md),
adding support for add, sub, mul for i8x16, i16x8, i32x4, and f32x4.

The spec is WIP, and might change in the near future.

Patch by João Porto

Differential Revision: https://reviews.llvm.org/D22686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277543 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:16:09 +00:00
Tim Northover
d022ddb138 ARM: only form SMMLS when SUBE flags unused.
In this particular example we wouldn't want the smmls anyway (the value is
actually unused), but in general smmls does not provide the required flags
register so if that SUBE result is used we can't replace it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277541 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 23:12:36 +00:00
Kevin Enderby
d5adfbcabc More fixes to get good error messages for bad archives.
Fixed the last incorrect uses of llvm_unreachable() in the code
which were actually just cases of errors in the input Archives.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277540 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:58:55 +00:00
Sanjay Patel
a1c5f9f963 [InstCombine] replace dyn_casts with matches; NFCI
Clean-up before changing this to allow folds for vectors.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277538 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:38:33 +00:00
Kostya Serebryany
2ca02f6ea0 [sanitizer] Implement a __asan_default_options() equivalent for Scudo
Summary:
Currently, the Scudo Hardened Allocator only gets its flags via the SCUDO_OPTIONS environment variable.
With this patch, we offer the opportunity for programs to define their own options via __scudo_default_options() which behaves like __asan_default_options() (weak symbol).
A relevant test has been added as well, and the documentation updated accordingly.
I also used this patch as an opportunity to rename a few variables to comply with the LLVM naming scheme, and replaced a use of Report with dieWithMessage for consistency (and to avoid a callback).

Reviewers: llvm-commits, kcc

Differential Revision: https://reviews.llvm.org/D23018

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277536 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:25:38 +00:00
Matt Arsenault
94166e75ac AMDGPU: fdiv -1, x -> rcp -x
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277535 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:25:04 +00:00
Piotr Padlewski
c2a3bce22d Imported statistics types changes
Reviewers: tejohnson, eraman

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277534 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:18:47 +00:00
George Burgess IV
4968ef3366 [CFLAA] Be more conservative with values we haven't seen.
There were issues with simply reporting AttrUnknown on
previously-unknown values in CFLAnders. So, we now act *entirely*
conservatively for values we haven't seen before. As in the prior patch
(r277362), writing a lit test for this isn't exactly trivial. If someone
wants a test badly, I'm willing to try to write one.

Patch by Jia Chen.

Differential Revision: https://reviews.llvm.org/D23077


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277533 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 22:17:25 +00:00
Daniel Berlin
35142a98ef Move to having a single real instructionClobbersQuery
Summary: We really want to move towards MemoryLocOrCall (or fix AA) everywhere, but for now, this lets us have a single instructionClobbersQuery.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23072

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277530 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:57:52 +00:00
Rui Ueyama
9222178199 PDB: Mark extended file pages as free by default.
BitVector::extend initializes extended bits as true by default.
That is not desirable because new pages should be initially free.

Differential Revision: https://reviews.llvm.org/D23048

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277529 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:56:37 +00:00
Krzysztof Parzyszek
8d96db9629 [Hexagon] Recognize vcombine in copy propagation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277528 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:49:20 +00:00
Michael Zolotukhin
559102f2be [LoopUnroll] Fix a PowerPC test broken by r277524.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277527 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:43:25 +00:00
Michael Zolotukhin
9ef092dcb0 [LoopUnroll] Switch the default value of -unroll-runtime-epilog back to its original value.
As agreed in post-commit review of r265388, I'm switching the flag to
its original value until the 90% runtime performance regression on
SingleSource/Benchmarks/Stanford/Bubblesort is addressed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277524 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:24:14 +00:00
Lang Hames
f8cfb2fa65 [lli] Add the ability for OrcLazyJIT to accept multiple input modules.
LLI already supported passing multiple input modules to MCJIT via the
-extra-module option. This patch adds the plumbing to pass these modules to
the OrcLazy JIT too.

This functionality will be used in an upcoming test case for weak symbol
handling.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277521 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 21:00:40 +00:00
Artem Belevich
23d7717d3d [NVPTX] remove unnecessary named metadata update that happens to break debug info.
Also added test case to verify IR changes done by NVPTXGenericToNVVM pass.

Differential Revision: https://reviews.llvm.org/D22837

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277520 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:58:24 +00:00
Wei Mi
ba9543ccae [LoopVectorize] Change comment for isOutOfScope in collectLoopUniforms, NFC
Update comment for isOutOfScope and add a testcase for uniform value being used
out of scope.

Differential Revision: https://reviews.llvm.org/D23073


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277515 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:27:49 +00:00
Tim Northover
22b561a27e AArch64: properly calculate cmpxchg status in FastISel.
We were relying on the misleadingly-names $status result to actually be the
status. Actually it's just a scratch register that may or may not be valid (and
is the inverse of the real ststus anyway). Success can be determined by
comparing the value loaded against the one we wanted to see for "cmpxchg
strong" loops like this.

Should fix PR28819.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277513 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:22:36 +00:00
Daniel Berlin
558bab8534 Fixes for post-commit review comments on r277480
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277510 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 20:02:21 +00:00
Sanjoy Das
55fcee64a9 [IRCE] Rename variable; NFC
There is nothing "Original" about "OriginalLoopInfo".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277506 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:32:01 +00:00
Sanjoy Das
ee53c92338 [IRCE] Preserve DomTree and LCSSA
This changes IRCE to "preserve" LCSSA and DomTree by recomputing them.
It still does not preserve LoopSimplify.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277505 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:31:54 +00:00
Nicolai Haehnle
87d298325f AMDGPU: Stay in WQM for non-intrinsic stores
Summary:
Two types of stores are possible in pixel shaders: stores to memory that are
explicitly requested at the API level, and stores that are an implementation
detail of register spilling or lowering of arrays.

For the first kind of store, we must ensure that helper pixels have no effect
and hence WQM must be disabled. The second kind of store must always be
executed, because the written value may be loaded again in a way that is
relevant for helper pixels as well -- and there are no externally visible
effects anyway.

This is a candidate for the 3.9 release branch.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, kzhuravl, llvm-commits

Differential Revision: https://reviews.llvm.org/D22675

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277504 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:31:14 +00:00
Albert Gutowski
3db929534b test commit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277503 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:25:17 +00:00
Michael Zolotukhin
bc280d0f4f [LoopUnroll] Ensure we create prolog loops in simplified form.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277502 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:19:31 +00:00
Nirav Dave
0fa8922515 Fix handling of end-of-line preprocessor comments Attempt 2
Attempt 2: Retryign after Tsan.mman test fix.

Attempt 1: Recommitting after fixing test.

When parsing assembly where the line comment syntax is not hash, the
lexer cannot distinguish between hash's that start a hash line comment
and one that is part of an assembly statement and must be distinguished
during parsing. Previously, this was incompletely handled by not checking
for EndOfStatement at the end of statements and interpreting hash
prefixed statements as comments.

Change EndOfStatement Parsing to check for Hash comments and reintroduce
Hash statement parsing to catch previously handled cases.

Reviewers: rnk, majnemer

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23017

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277501 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:17:54 +00:00
Nicolai Haehnle
a8461187eb AMDGPU: Track physical registers in SIWholeQuadMode
Summary:
There are cases where uniform branch conditions are computed in VGPRs, and
we didn't correctly mark those as WQM.

The stray change in basic-branch.ll is because invoking the LiveIntervals
analysis leads to the detection of a dead register that would otherwise not
be seen at -O0.

This is a candidate for the 3.9 branch, as it fixes a possible hang.

Reviewers: arsenm, tstellarAMD, mareko

Subscribers: arsenm, llvm-commits, kzhuravl

Differential Revision: https://reviews.llvm.org/D22673

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277500 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:17:37 +00:00
Ahmed Bougacha
af5f07500c [AArch64][GlobalISel] Replace test REQUIRES with lit.local.cfg. NFC.
I forgot the REQUIRES once (see r277486).
Let's prevent it from happening again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277499 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:04:29 +00:00
Ahmed Bougacha
9ce2f98aaa [AArch64] Remove useless 'import re' from CodeGen lit.local.cfg. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277498 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 19:04:25 +00:00
Krzysztof Parzyszek
1b1291fbbb [Hexagon] Prefer _io over _rr for 64-bit store with constant offset
Identify patterns where the address is aligned to an 8-byte boundary,
but both the base address and the constant offset are both proper
multiples of 4. In such cases, extract Base+4 into a separate instruc-
tion, and use S2_storerd_io, instead of using S4_storerd_rr.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277497 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 18:50:05 +00:00
Krzysztof Parzyszek
aeac124408 [Hexagon] Remove unused option
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277496 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 18:39:32 +00:00
Krzysztof Parzyszek
a4e94ebbb2 [Hexagon] Improvements to address mode checks in TargetLowering
- Implement getOptimalMemOpType.
- Check BaseOffset in isLegalAddressingMode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277494 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 18:34:31 +00:00
Nirav Dave
c37e7b92f8 [MC] Fix Intel Operand assembly parsing for .set ids
Recommitting after fixing overaggressive fastpath return in parsing.

Fix intel syntax special case identifier operands that refer to a constant
(e.g. .set <ID> n) to be interpreted as immediate not memory in parsing.

Associated commit to fix clang test commited shortly.

Reviewers: rnk

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D22585

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277489 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 17:56:03 +00:00
Ahmed Bougacha
93a0b1235f [AArch64][GlobalISel] Add REQUIRES: global-isel to verifier tests.
I thought the directory had a lit.local.cfg, but it doesn't.
I'll add one, but for now, add the REQUIRES line. While there,
move the triple into the IR and add a datalayout.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277486 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 17:19:35 +00:00
Daniel Berlin
c1f8f3a65f MSVC 2013 does not implement C++11 unions properly, so remove the anoymous union for now,
and leave a FIXME.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277485 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:59:51 +00:00
Ahmed Bougacha
9618468f1c [GlobalISel] Set the Selected MF property.
None of GlobalISel requires the property, but this lets us use the
verifier instead of rolling our own "all instructions selected" check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277484 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:49:25 +00:00
Ahmed Bougacha
35426be67b [GlobalISel] Verify Selected MF property.
After instruction selection, there should be no pre-isel generic
instructions remaining, nor should generic virtual registers be
used. Verify that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277483 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:49:22 +00:00
Ahmed Bougacha
fc114db3c4 [GlobalISel] Add Selected MachineFunction property.
Selected: the InstructionSelect pass ran and all pre-isel generic
instructions have been eliminated; i.e., all instructions are now
target-specific or non-pre-isel generic instructions (e.g., COPY).

Since only pre-isel generic instructions can have generic virtual register
operands, this also means that all generic virtual registers have been
constrained to virtual registers (assigned to register classes) and that
all sizes attached to them have been eliminated.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277482 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:49:19 +00:00
Daniel Berlin
c32071c252 Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670

Summary:
Rewrite the use optimizer to be less memory intensive and 50% faster.
Fixes PR28670

The new use optimizer works like a standard SSA renaming pass, storing
all possible versions a MemorySSA use could get in a stack, and just
tracking indexes into the stack.
This uses much less memory than caching N^2 alias query results.
It's also a lot faster.

The current version defers phi node walking to the normal walker.

Reviewers: george.burgess.iv

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23032

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277480 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:24:03 +00:00
Artur Pilipenko
e2e5c0738c [LVI] NFC. Sink a condition type check from the caller down to getValueFromCondition
This is a preparatory refactoring to support conditions other than ICmpInst.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277479 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:20:48 +00:00
Ahmed Bougacha
7abac75bf9 [GlobalISel] Set and require RegBankSelected MF property.
The InstructionSelect pass assumes that RegBankSelect ran; set the
property on all tests (thereby verifying the test inputs) and require
it in the pass.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277477 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:17:18 +00:00
Ahmed Bougacha
1f82c34de8 [GlobalISel] Verify RegBankSelected MF property.
RegBankSelected functions shouldn't have any generic virtual
register not assigned to a bank. Verify that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277476 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:17:15 +00:00
Ahmed Bougacha
31c3e4f363 [GlobalISel] Add RegBankSelected MachineFunction property.
RegBankSelected: the RegBankSelect pass ran and all generic virtual
registers have been assigned to a register bank.

This lets us enforce certain invariants across passes.
This property is GlobalISel-specific, but is always available.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277475 91177308-0d34-0410-b5e6-96231b3b80d8
2016-08-02 16:17:10 +00:00