Commit Graph

181297 Commits

Author SHA1 Message Date
Fangrui Song
3228596b4c Cleanup: llvm::bsearch -> llvm::partition_point after r364719
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364720 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-30 11:19:56 +00:00
Fangrui Song
726837ec5a [ADT] Implement llvm::bsearch() with std::partition_point()
Summary:
Delete the begin-end form because the standard std::partition_point
can be easily used as a replacement.

The ranges-style llvm::bsearch will be renamed to llvm::partition_point
in the next clean-up patch.

The name "bsearch" doesn't meet people's expectation because in C:

> If two or more members compare equal, which member is returned is unspecified.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D63718

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364719 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-30 09:17:59 +00:00
Craig Topper
146c283337 [X86] Custom lower AVX masked loads to masked load and vselect instead of selecting a maskmov+vblend during isel.
AVX masked loads only support 0 as the value for masked off elements.
So we need an extra blend to support other values. Previously we
expanded the masked load to two instructions with isel patterns.
With this patch we now insert the vselect during lowering and it
will be separately selected as a blend.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364718 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-30 06:46:37 +00:00
Craig Topper
eb4bea11d2 [SelectionDAG] Use the memory VT instead of result VT for FoldingSet profiling in getMaskedLoad/getMaskedStore.
This matches what is done by the Profile function. Otherwise CSE
won't work properly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364717 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-30 06:46:33 +00:00
Nikita Popov
3f463ae38e [LFTR] Rephrase getLoopTest into "based-on" check; NFCI
What we want to know here is whether we're already using this value
for the loop condition, so make the query about that. We can extend
this to a more general "based-on" relationship, rather than a direct
icmp use later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364715 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 15:12:59 +00:00
Sanjay Patel
5a07a49365 [InstCombine] canonicalize fmin/fmax to LLVM intrinsics minnum/maxnum
This transform came up in D62414, but we should deal with it first.
We have LLVM intrinsics that correspond exactly to libm calls (unlike
most libm calls, these libm calls never set errno).
This holds without any fast-math-flags, so we should always canonicalize
to those intrinsics directly for better optimization.
Currently, we convert to fcmp+select only when we have FMF (nnan) because
fcmp+select does not preserve the semantics of the call in the general case.

Differential Revision: https://reviews.llvm.org/D63214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364714 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 14:28:54 +00:00
Nikita Popov
e2e907a75f [LFTR] Remove unnecessary latch check; NFCI
The whole indvars pass works on loops in simplified form, so there
is always a unique latch. Convert the condition into an assertion
in needsLFTR (though we also assert this in later LFTR functions).

Additionally update the comment on getLoopTest() now that we are
dealing with multiple exits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364713 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 12:41:02 +00:00
Roman Lebedev
40b63d7e12 [InstCombine] Shift amount reassociation (PR42391)
Summary:
Given pattern:
`(x shiftopcode Q) shiftopcode K`
we should rewrite it as
`x shiftopcode (Q+K)`  iff `(Q+K) u< bitwidth(x)`
This is valid for any shift, but they must be identical.

* https://rise4fun.com/Alive/9E2
* exact on both lshr => exact https://rise4fun.com/Alive/plHk
* exact on both ashr => exact https://rise4fun.com/Alive/QDAA
* nuw on both shl => nuw https://rise4fun.com/Alive/5Uk
* nsw on both shl => nsw https://rise4fun.com/Alive/0plg

Should fix [[ https://bugs.llvm.org/show_bug.cgi?id=42391 | PR42391]].

Reviewers: spatel, nikic, RKSimon

Reviewed By: nikic

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63812

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364712 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 11:51:50 +00:00
Roman Lebedev
e30b1c0c22 [IR][Patternmatch] Add m_SpecificInt_ULT() predicate
Summary:
Match an integer or vector with every element unsigned less than the
Threshold. For vectors, this includes constants with undefined elements.

FIXME: is it worth generalizing this to simply take ICmpInst::Predicate?

Reviewers: craig.topper, spatel, nikic

Reviewed By: spatel

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63811

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364711 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 11:51:37 +00:00
Dmitry Venikov
78409abb65 [APInt] Fix getBitsNeeded for INT_MIN values
Summary: This patch fixes behaviour of APInt::getBitsNeeded for INT_MIN 10 bits values.

Reviewers: regehr, RKSimon

Reviewed By: RKSimon

Subscribers: grandinj, dexonsmith, kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63691

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364710 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 11:38:12 +00:00
Nikita Popov
d6d7595593 [LFTR] Fix post-inc pointer IV with truncated exit count (PR41998)
Fixes https://bugs.llvm.org/show_bug.cgi?id=41998. Usually when we
have a truncated exit count we'll truncate the IV when comparing
against the limit, in which case exit count overflow in post-inc
form doesn't matter. However, for pointer IVs we don't do that, so
we have to be careful about incrementing the IV in the wide type.

I'm fixing this by removing the IVCount variable (which was
ExitCount or ExitCount+1) and replacing it with a UsePostInc flag,
and then moving the actual limit adjustment to the individual cases
(which are: pointer IV where we add to the wide type, integer IV
where we add to the narrow type, and constant integer IV where we
add to the wide type).

Differential Revision: https://reviews.llvm.org/D63686

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364709 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 09:24:12 +00:00
Sam Clegg
45adfa50b3 Partial revert of "[llvm-ar] Document response file support in --help"
This is partial revert of 70a8027c60fe1f95e8a8a1ff6575ebf8778d3544.

The test apparently failed on win32 bots due to the way slashes in
pathnames are handled.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364705 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 01:53:26 +00:00
Matt Arsenault
8ab3aebea9 AMDGPU/GlobalISel: Add some more tests for icmp select
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364703 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:55:16 +00:00
Matt Arsenault
fbcfc11ccf AMDGPU/GlobalISel: RegBankSelect for update.dpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364701 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:44:36 +00:00
Matt Arsenault
943e70b2b9 AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.dec
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364699 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:39:20 +00:00
Matt Arsenault
7846e1a4c8 AMDGPU/GlobalISel: RegBankSelect for some DS intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364698 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:33:13 +00:00
Matt Arsenault
2c47ef0858 AMDGPU/GlobalISel: RegBankSelect for some easy intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364697 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:29:56 +00:00
Matt Arsenault
6443be3e79 AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364696 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:28:52 +00:00
Matt Arsenault
255a34f4a6 AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmas
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364695 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:25:53 +00:00
Matt Arsenault
f5bebba122 AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsics
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364694 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:22:28 +00:00
Philip Reames
b088165d46 [IndVars] Remove a bit of manual constant folding [NFC]
SCEV is more than capable of folding (add x, trunc(0)) to x.  



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364693 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-29 00:19:31 +00:00
Matt Arsenault
e8752a14e2 AMDGPU: Add baseline test for packed shufflevector
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364691 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 23:43:40 +00:00
Wouter van Oortmerssen
760081b314 [WebAssembly] Assembler: support .int16/32/64 directives.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63959

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364689 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 22:20:33 +00:00
Wouter van Oortmerssen
8f0f64884c [WebAssembly] Allow @object in .type directives.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63955

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364688 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 21:53:11 +00:00
Sanjay Patel
9444c0b43c [x86] remove stale comment about cmov; NFC
The cmov node used to sometimes return a glue result (and that's what
'flag' meant in this context), but that was removed with D38664.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364687 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 21:45:55 +00:00
Cameron McInally
edccd2d575 [NFC][NewGVN] Explicitly check fpmath metadata in fpmath.ll
Suggested in D63933.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364685 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 21:39:08 +00:00
Sanjay Patel
543603b46a [Lanai] auto-generate complete test checks; NFC
This file will fail with a common codegen transform that
I'm looking at, and I can't tell if that's an improvement
or regression based on the sparse checking.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364684 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 20:45:32 +00:00
Wouter van Oortmerssen
438ae9d393 [WebAssembly] Assembler: Allow offsets and p2align in symbol load.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63951

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364682 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 20:31:13 +00:00
Wouter van Oortmerssen
878043c39c [WebAssembly] Assembler: Improve section parsing.
Reviewers: sbc100

Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63947

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364681 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 20:29:16 +00:00
Cameron McInally
55848f6897 [NewGVN] Add unary FNeg support to NewGVN pass
Differential Revision: https://reviews.llvm.org/D63933

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364680 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 20:09:32 +00:00
Cameron McInally
af4521393e [GVNSink] Add unary FNeg support to GVNSink pass
Differential Revision: https://reviews.llvm.org/D63900

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364678 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 19:57:31 +00:00
Erik Pilkington
aa29685fed [demangle] Support for C++2a char8_t
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364677 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 19:54:19 +00:00
Brad Smith
b828a021ac Default to Secure PLT on PPC for musl libc.
This matches the default settings of clang.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364675 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 19:48:31 +00:00
Sam Clegg
ddc7452fdd [llvm-ar] Document response file support in --help
Also a test for this.

Differential Revision: https://reviews.llvm.org/D63836

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364673 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 18:48:05 +00:00
Lang Hames
99fc4ea417 Re-apply r364600 with fixes.
Fix: MachO/X86_64_RELOC_GOT is a 32-bit reloc, so only compare 32 bits.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364672 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 18:36:59 +00:00
Rainer Orth
57965ba220 [unittests][Support] Fix LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions on Solaris
LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions currently
FAILs on Solaris:

  FAIL: LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions (2940 of 51555)
  ******************** TEST 'LLVM-Unit :: Support/./SupportTests/FileSystemTest.permissions' FAILED ********************
  Note: Google Test filter = FileSystemTest.permissions
  [==========] Running 1 test from 1 test case.
  [----------] Global test environment set-up.
  [----------] 1 test from FileSystemTest
  [ RUN      ] FileSystemTest.permissions
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1705: Failure
  Value of: CheckPermissions(fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1712: Failure
  Value of: CheckPermissions(fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1719: Failure
  Value of: CheckPermissions(fs::all_read | fs::set_uid_on_exe | fs::set_gid_on_exe | fs::sticky_bit)
    Actual: false
  Expected: true
  /opt/llvm-buildbot/obj/llvm/llvm.src/unittests/Support/Path.cpp:1722: Failure
  Value of: CheckPermissions(fs::all_perms)
    Actual: false
  Expected: true
  [  FAILED  ] FileSystemTest.permissions (0 ms)
  [----------] 1 test from FileSystemTest (0 ms total)
  
  [----------] Global test environment tear-down
  [==========] 1 test from 1 test case ran. (1 ms total)
  [  PASSED  ] 0 tests.
  [  FAILED  ] 1 test, listed below:
  [  FAILED  ] FileSystemTest.permissions
  
   1 FAILED TEST

Checking with truss reveals that this is the same issue as on AIX and
documented in chmod(2):

  If the process is not a privileged process and the file is not a direc-
  tory, mode bit 01000 (S_ISVTX, the sticky bit) is cleared.

The following patch fixes this in the same way.  Tested on amd64-pc-solaris2.11.

Differential Revision: https://reviews.llvm.org/D63598


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364671 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 18:29:18 +00:00
Jinsong Ji
e09833c6e9 [UpdateChecks] Add support for armv7-apple-darwin
armv7-apple-darwin was not supported well, the script can't generate
checks.

https://reviews.llvm.org/D60601/new/#inline-568671

Differential Revision: https://reviews.llvm.org/D63939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364668 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 18:07:19 +00:00
Simon Pilgrim
08a4b34e50 [X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chain
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364667 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 17:57:32 +00:00
Peter Collingbourne
9e1d739445 hwasan: Remove the old frame descriptor mechanism.
Differential Revision: https://reviews.llvm.org/D63470

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364665 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 17:53:26 +00:00
Roman Lebedev
ae7898988a [NFC][Codegen] Revisit test coverage for X % C == 0 fold once more (add tests with '1' divisor)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364661 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 17:26:28 +00:00
Wouter van Oortmerssen
a8ce5edb5c [WebAssembly] Added visibility and ident directives to WasmAsmParser.
Summary:
These are output by clang -S, so can now be roundtripped thru clang.

(partially) fixes: https://bugs.llvm.org/show_bug.cgi?id=34544

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63901

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364658 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 16:51:06 +00:00
Roman Lebedev
0203679424 [NFC][InstCombine] Shift amount reassociation: revisit flag preservation tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364657 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 16:36:53 +00:00
Dmitry Preobrazhensky
539c69ef52 [AMDGPU][MC] Fix 2 for sanitizer failure in 364645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364656 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 16:28:46 +00:00
Sam Tebbs
a71ac42554 [ARM] Add support for the MVE long shift instructions
MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers.

The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl.

test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions.

Differential Revision: https://reviews.llvm.org/D63430

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364654 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:43:31 +00:00
Max Moroz
cdc939779e [llvm-cov[ Fix lcov coverage report contains functions from other compilation units.
Summary: Patch by Chuan Qiu (@eagleonhill).

Reviewers: Dor1s

Reviewed By: Dor1s

Subscribers: lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63571

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364653 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:38:25 +00:00
Roman Lebedev
4f9b5abd8a [NFC][InstCombine] Shift amount reassociation: add flag preservation test
As discussed in https://reviews.llvm.org/D63812#inline-569870
* exact on both lshr => exact https://rise4fun.com/Alive/plHk
* exact on both ashr => exact https://rise4fun.com/Alive/QDAA
* nuw on both shl => nuw https://rise4fun.com/Alive/5Uk
* nsw on both shl => nsw https://rise4fun.com/Alive/0plg

So basically if the same flag is set on both original shifts -> set it on new shift.
Don't think we can do anything with non-matching flags on shl.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364652 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:32:52 +00:00
Dmitry Preobrazhensky
c8753f157b [AMDGPU][MC] Fix for sanitizer failure in 364645
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364651 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:22:47 +00:00
Cameron McInally
aca088eadf [NFC][Float2Int] Pre-commit unary FNeg test to basic.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364649 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 15:12:15 +00:00
Cameron McInally
c57ffd6937 [NFC][NewGVN] Pre-commit unary FNeg test to fpmath.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364646 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 14:39:58 +00:00
Dmitry Preobrazhensky
3c357a49a3 [AMDGPU][MC] Enabled constant expressions as operands of sendmsg
See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62735

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@364645 91177308-0d34-0410-b5e6-96231b3b80d8
2019-06-28 14:14:02 +00:00