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Author SHA1 Message Date
Chris Lattner
065421f99f Implement CodeGen/X86/2007-03-24-InlineAsmMultiRegConstraint.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35324 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:18:14 +00:00
Chris Lattner
e4e2e18f47 new testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35323 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:17:58 +00:00
Chris Lattner
4234f57fa0 switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35322 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:14:49 +00:00
Reid Spencer
2b81207b4b More APIntification: 
* Convert the last use of a uint64_t that should have been an APInt.
* Change ComputeMaskedBits to have a const reference argument for the Mask
  so that recursions don't cause unneeded temporaries. This causes temps
  to be needed in other places (where the mask has to change) but this
  change optimizes for the recursion which is more frequent.
* Remove two instances of &ing a Mask with getAllOnesValue. Its not
  needed any more because APInt is accurate in its bit computations.
* Start using the getLowBitsSet and getHighBits set methods on APInt
  instead of shifting. This makes it more clear in the code what is
  going on.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35321 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:03:12 +00:00
Chris Lattner
1439352ece Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35320 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 02:01:03 +00:00
Chris Lattner
188b9fe834 enforce the proper range for the i386 N constraint. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35319 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 01:57:35 +00:00
Chris Lattner
7cd5e07f3d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35318 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 01:44:57 +00:00
Chris Lattner
9a4fdfac3d new testcase 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35317 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 01:44:40 +00:00
Reid Spencer
5b9f2d6186 Fix a typo in a comment. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35316 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 01:13:46 +00:00
Reid Spencer
a1689ea60e Actually, for getHighBitsSet and getLowBitsSet, don't make a 0 bit size 
illegal. Instead do the 0 valued construction for the user. This is because
the caller may not know (or care to check) that the number of bits set is
zero.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35315 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-25 00:01:47 +00:00
Chris Lattner
42593e69e2 fix a regression on vector or instructions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35314 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:56:43 +00:00
Reid Spencer
758d1bc919 Make it illegal to set 0 bits in getHighBitsSet and getLowBitsSet. For that 
they should have used the uint64_t constructor. This avoids causing
undefined results via shifts by the word size when the bit width is an
exact multiple of the word size.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35313 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:47:58 +00:00
Reid Spencer
5b7e659e22 In the getBitsSet function, don't optimize for a common case that is 
already covered by getLowBitsSet (i.e. when loBits==0). Consequently, remove
the default value for loBits and reorder the arguments to the more natural
loBits, hiBits order. This makes it more clear that this function is for bit
groups in the middle of the bit width and not towards one end or the other.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35312 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:42:47 +00:00
Reid Spencer
ca76fc2cd3 Don't invoke undefined behavior in shifts in the functions getHighBitsSet 
and getLowBitsSet.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35311 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:35:54 +00:00
Reid Spencer
8f969ee62c Implement the getBitsSet function. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35310 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:27:48 +00:00
Reid Spencer
3f3ee6e588 Remove the last vestiges of this directory. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35309 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:07:49 +00:00
Reid Spencer
8da7d65b83 Implement the getHighBitsSet and getLowBitsSet functions. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35308 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 23:05:35 +00:00
Reid Spencer
013263f7b0 Get the signs in the right place! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35307 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 22:50:43 +00:00
Reid Spencer
64f5c6c357 Fix a link. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35306 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 22:40:44 +00:00
Reid Spencer
d3af825d29 Undo the last change and make this really implement remainder and not 
modulus. The previous change was a result of incorrect documentation in
the LangRef.html.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35305 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 22:37:23 +00:00
Reid Spencer
9f992aec98 Flip the srem tests around. Previous commit was to correct an apparent 
bug in the srem implementation. Turns out it was a documentation bug
instead.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35304 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 22:34:10 +00:00
Reid Spencer
c9fdfc8e9f Correct the description of srem. remainder follows the dividend not the 
divisor!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35303 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 22:23:39 +00:00
Reid Spencer
53c9520b23 Correct the implementation of srem to be remainder, not modulus. The sign of 
the result must follow the sign of the divisor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35302 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 21:56:22 +00:00
Reid Spencer
5957d8ffd8 Fix incorrect test cases for srem. The definition of srem is a remainder so 
that the sign of the result follows the sign of the divisor.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35301 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 21:55:26 +00:00
Reid Spencer
7ac2f81e49 Clean up this interface: 
1. Group similar methods into doxygen groups
2. Reorganize the groups into a consist flow.
3. Significantly improve the quality of the documentation on several methods
4. Rewrite srem and sdiv to eliminate a copy and improve readability.
5. Eliminate unneeded forward references.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35300 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 18:09:18 +00:00
Chris Lattner
82dcb4fe23 don't rely on ADL 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35299 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 17:37:03 +00:00
Chris Lattner
0d3988f408 add a valuetype for v1i64, which is needed by mmx. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35298 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 17:36:26 +00:00
Zhou Sheng
00f436c5bc Make some codes more efficient. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35297 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 15:34:37 +00:00
Chris Lattner
1a77a556cd add a bad case evan though of. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35296 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 06:01:32 +00:00
Reid Spencer
f244252740 For PR1205: 
Convert some calls to ConstantInt::getZExtValue() into getValue() and
use APInt facilities in the subsequent computations.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35294 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 00:42:08 +00:00
Evan Cheng
dae54ce7fc Adjust offset to compensate for big endian machines. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35293 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-24 00:02:43 +00:00
Anton Korobeynikov
3b5ee73a13 Autodetect MMX & SSE stuff for AMD processors 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35292 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 23:46:48 +00:00
Bill Wendling
b172ab0533 This is dead. DEAD I tells you!! 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35291 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 22:42:04 +00:00
Bill Wendling
b8440a0c39 PR1260: 
Add final support to get the QT example to compile.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35290 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 22:35:46 +00:00
Evan Cheng
e177e307fc Make sure SEXTLOAD of the specific type is supported on the target. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35289 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 22:13:36 +00:00
Reid Spencer
aa04035229 Add more test cases for APIntified InstCombine. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35288 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 21:57:47 +00:00
Reid Spencer
2ec619a29a For PR1205: 
* APIntify visitAdd and visitSelectInst
* Remove unused uint64_t versions of utility functions that have been
  replaced with APInt versions.
This completes most of the changes for APIntification of InstCombine. This
passes llvm-test and llvm/test/Transforms/InstCombine/APInt.

Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35287 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 21:24:59 +00:00
Evan Cheng
b37b80ce46 Also replace uses of SRL if that's also folded during ReduceLoadWidth(). 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35286 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 20:55:21 +00:00
Reid Spencer
5d787bb93e Add test case for testing InstCombine with arbitrary precision integer 
types. These tests mimic the integer test cases in the normal InstCombine
test suite but use "strange" integer bit widths.

Most tests written by Zhou Sheng, a few by me.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35284 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 20:48:34 +00:00
Reid Spencer
bca0e38baa For PR1205: 
APIntify visitDiv, visitMul and visitRem.

Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35283 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 20:05:17 +00:00
Chris Lattner
2c7718a539 switch AddReachableCodeToWorklist from being recursive to being iterative. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35282 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 19:17:18 +00:00
Reid Spencer
b35ae0371a For PR1205: 
APIntify several utility functions supporting logical operators and shift
operators.

Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35281 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 18:46:34 +00:00
Dan Gohman
423c2260f9 Add the 'explicit' keyword to several constructors that accept one 
argument that don't appear intended as implicit-conversion operators.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35280 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 18:44:11 +00:00
Duncan Sands
b819a2b5fe Test handling of switches with wide case ranges. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35279 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 07:17:52 +00:00
Reid Spencer
b8f1c1657f Fix constant fold of div by zero and rem by zero to match IEEE 754 
requirements. We must return NaN in some cases and correctly signed
infinity in other cases. Passes CFP2006 (not that that says much).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35277 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 05:33:23 +00:00
Zhou Sheng
f62cc9f9e5 Make the "KnownZero ^ TypeMask" computation just once. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35276 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 03:13:21 +00:00
Zhou Sheng
9c636fe6f2 Simplify the code. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35275 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 02:39:25 +00:00
Evan Cheng
0b063def98 A couple of bug fixes for reducing load width xform: 
1. Address offset is in bytes.
2. Make sure truncate node uses are replaced with new load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35274 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-23 02:16:52 +00:00
Reid Spencer
a03d45fa88 For PR1205: 
APInt support for logical operators in visitAnd, visitOr, and visitXor.

Patch by Zhou Sheng.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35273 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 22:19:58 +00:00
Duncan Sands
28ecc1a6fa The -funcresolve and -raise options no longer exist. 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35272 91177308-0d34-0410-b5e6-96231b3b80d8
 2007-03-22 21:06:50 +00:00