llvm-readobj "non-standard" flags `--mips-plt-got`, `--mips-abi-flags`,
`--mips-reginfo`, and `--mips-options` are superseded by the `--arch-specific`
flag and can be removed now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373590 91177308-0d34-0410-b5e6-96231b3b80d8
Old options `--mips-plt-got`, `--mips-abi-flags`, '--mips-reginfo`,
and `--mips-options` wiil be deleted in a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373588 91177308-0d34-0410-b5e6-96231b3b80d8
Adds support to AArch64FrameLowering to allocate fixed-stack SVE objects.
The focus of this patch is purely to allow the stack frame to
allocate/deallocate space for scalable SVE objects. More dynamic
allocation (at compile-time, i.e. determining placement of SVE objects
on the stack), or resolving frame-index references that include
scalable-sized offsets, are left for subsequent patches.
SVE objects are allocated in the stack frame as a separate region below
the callee-save area, and above the alignment gap. This is done so that
the SVE objects can be accessed directly from the FP at (runtime)
VL-based offsets to benefit from using the VL-scaled addressing modes.
The layout looks as follows:
+-------------+
| stack arg |
+-------------+
| Callee Saves|
| X29, X30 | (if available)
|-------------| <- FP (if available)
| : |
| SVE area |
| : |
+-------------+
|/////////////| alignment gap.
| : |
| Stack objs |
| : |
+-------------+ <- SP after call and frame-setup
SVE and non-SVE stack objects are distinguished using different
StackIDs. The offsets for objects with TargetStackID::SVEVector should be
interpreted as purely scalable offsets within their respective SVE region.
Reviewers: thegameg, rovka, t.p.northover, efriedma, rengolin, greened
Reviewed By: efriedma
Differential Revision: https://reviews.llvm.org/D61437
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373585 91177308-0d34-0410-b5e6-96231b3b80d8
This improves broadcast load folding of i64 elements on 32-bit
targets where i64 isn't legal.
Previously we had to represent these as vXf64 vbroadcast_loads and
a bitcast to vXi64. But we didn't have any isel patterns
looking for that.
This also allows us to remove or simplify some isel patterns that
were looking for bitcasted vbroadcast_loads.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373566 91177308-0d34-0410-b5e6-96231b3b80d8
Newer cmakes appear to be more flexible w.r.t object libraries. Convert to
a static library so that it works with older cmakes too
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373555 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This will handle expansion of C++ fragments in the declarative combiner
including custom predicates, and escapes into C++ to aid the migration
effort.
Reviewers: bogner, volkan
Subscribers: mgorny, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68288
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373551 91177308-0d34-0410-b5e6-96231b3b80d8
When SIFixSGPRCopies attempts to fix an illegal copy from vector to
scalar register it calls moveToVALU(). A copy from an agpr to sgpr
becomes a copy from agpr to agpr, which may result in the illegal
register class at a use of this copy.
Solution is to copy it always into a vgpr. This may result in a
subsequent copy into an agpr if that is what really needed, however
should not happen too often and likely will be folded later.
The opposite situation may not happen because an sgpr is always
illegal where agpr is legal, so such user instructions may not
exist.
Differential Revision: https://reviews.llvm.org/D68358
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373544 91177308-0d34-0410-b5e6-96231b3b80d8
This is unlikely to be the root cause for the windows bot failures but
it would explain the stack trace seen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373543 91177308-0d34-0410-b5e6-96231b3b80d8
https://rise4fun.com/Alive/8BY - valid for lshr+trunc+variable sext
https://rise4fun.com/Alive/7jk - the variable sext can be redundant
https://rise4fun.com/Alive/Qslu - 'exact'-ness of first shift can be preserver
https://rise4fun.com/Alive/IF63 - without trunc we could view this as
more general "drop redundant mask before right-shift",
but let's handle it here for now
https://rise4fun.com/Alive/iip - likewise, without trunc, variable sext can be redundant.
There's more patterns for sure - e.g. we can have 'lshr' as the final shift,
but that might be best handled by some more generic transform, e.g.
"drop redundant masking before right-shift" (PR42456)
I'm singling-out this sext patch because you can only extract
high bits with `*shr` (unlike abstract bit masking),
and i *know* this fold is wanted by existing code.
I don't believe there is much to review here,
so i'm gonna opt into post-review mode here.
https://bugs.llvm.org/show_bug.cgi?id=43523
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373542 91177308-0d34-0410-b5e6-96231b3b80d8
Brings this struct in line with the RangeSpan class so they might
eventually be used by common template code for generating range/loc
lists with less duplicate code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373540 91177308-0d34-0410-b5e6-96231b3b80d8
bcopy is still widely used mainly for network apps. Sadly, LLVM has no optimizations for bcopy, but there are some for memmove.
Since bcopy == memmove, it is profitable to transform bcopy to memmove and use current optimizations for memmove for free here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373537 91177308-0d34-0410-b5e6-96231b3b80d8
If the vselect result type needs to be split, it will try to
also try to split the condition if it happens to be a setcc.
With avx512 where k-registers are legal, its probably better
to just use a kshift to split the mask register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373536 91177308-0d34-0410-b5e6-96231b3b80d8
This is an effort to make RangeSpan and DebugLocStream::Entry more
similar to share code for their emission (to reuse the more complicated
code for using (& choosing when to use) base address selection entries,
etc).
It didn't seem like this struct was worth the complexity of
encapsulation - when the members could be initialized by the ctor to any
value (no validation) and the type is assignable (so there's no
mutability or other constraint being implemented by its interface).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373533 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
This is the first of a series of patches extracted from a much bigger WIP
patch. It merely establishes the tblgen pass and the way empty combiner
helpers are declared and integrated into a combiner info.
The tablegen pass takes a -combiners option to select the combiner helper
that will be generated. This can be given multiple values to generate
multiple combiner helpers at once. Doing so helps to minimize parsing
overhead.
The reason for creating a GlobalISel subdirectory in utils/TableGen is that
there will be quite a lot of non-pass files (~15) by the time the patch
series is done.
Reviewers: volkan
Subscribers: mgorny, hiraditya, simoncook, Petar.Avramovic, s.egerton, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68286
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373527 91177308-0d34-0410-b5e6-96231b3b80d8
The cause for the revert should be fixed by r373513 /
a80b6c15425f82521c624ff24c5c0a34cd534d54
This reverts commit 47dbcbd8ec6bf6c0b9cbe5811e81a37cc55e73ef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373522 91177308-0d34-0410-b5e6-96231b3b80d8
Store rlwinm Rx, Ry, 32, 0, 31 as rlwinm Rx, Ry, 0, 0, 31 and store
rldicl Rx, Ry, 64, 0 as rldicl Rx, Ry, 0, 0. Otherwise SH field is overflow and
fails assertion in assembly printing stage.
Differential Revision: https://reviews.llvm.org/D66991
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373519 91177308-0d34-0410-b5e6-96231b3b80d8
The anonymous namespace starts out (incorrectly) indented but isn't
indented from the TimeRegionsOpt declaration onwards.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373516 91177308-0d34-0410-b5e6-96231b3b80d8
Terminators like invoke can have users outside the current basic block.
We have to replace those users with undef, before replacing the
terminator.
This fixes a crash exposed by rL373430.
Reviewers: brzycki, asbirlea, davide, spatel
Reviewed By: asbirlea
Differential Revision: https://reviews.llvm.org/D68327
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373513 91177308-0d34-0410-b5e6-96231b3b80d8
MemoryPhis should be added in the IDF of the blocks newly gaining Defs.
This includes the blocks that gained a Phi and the block gaining a Def,
if the block did not have one before.
Resolves PR43427.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373505 91177308-0d34-0410-b5e6-96231b3b80d8
The previous code tried to do a trick where we would extract the subvector from the location we were inserting. Then xor that with the new value. Take the xored value and clear out the bits above the subvector size. Then shift that xored subvector to the insert location. And finally xor that with the original vector. Since the old subvector was used in both xors, this would leave just the new subvector at the inserted location. Since the surrounding bits had been zeroed no other bits of the original vector would be modified.
Unfortunately, if the old subvector came from undef we might aggressively propagate the undef. Then we end up with the XORs not cancelling because they aren't using the same value for the two uses of the old subvector. @bkramer gave me a case that demonstrated this, but we haven't reduced it enough to make it easily readable to see what's happening.
This patch uses a safer, but more costly approach. It isolate the bits above the insertion and bits below the insert point and ORs those together leaving 0 for the insertion location. Then widens the subvector with 0s in the upper bits, shifts it into position with 0s in the lower bits. Then we do another OR.
Differential Revision: https://reviews.llvm.org/D68311
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373495 91177308-0d34-0410-b5e6-96231b3b80d8
Summary:
64-bit WebAssembly (wasm64) is not specified and not supported in the
WebAssembly backend. We do have support for it in clang, however, and
we would like to keep that support because we expect wasm64 to be
specified and supported in the future. For now add an error when
trying to use wasm64 from the backend to minimize user confusion from
unexplained crashes.
Reviewers: aheejin, dschuff, sunfish
Subscribers: sbc100, jgravelle-google, hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D68254
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@373493 91177308-0d34-0410-b5e6-96231b3b80d8
