142960 Commits

Author SHA1 Message Date
Simon Pilgrim
39e9d60ebd [CostModel][X86] Tidyup arithmetic costs code. NFCI.
Remove unnecessary braces, remove one use variables and keep LUTs to similar naming convention.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291187 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 22:48:02 +00:00
Kostya Serebryany
93bacfd838 [libFuzzer] improve error handling during the merge (handle various IO failures)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291182 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 22:05:47 +00:00
Geoff Berry
156afea258 [AArch64] Fold some filled/spilled subreg COPYs
Summary:
Extend AArch64 foldMemoryOperandImpl() to handle folding spills of
subreg COPYs with read-undef defs like:

  %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64:%vreg0

by widening the spilled physical source reg and generating:

  STRXui %XZR <fi#0>

as well as folding fills of similar COPYs like:

  %vreg0:sub_32<def,read-undef> = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1

by generating:

  %vreg0:sub_32<def,read-undef> = LDRWui <fi#0>

Reviewers: MatzeB, qcolombet

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D27425

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291180 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 21:51:42 +00:00
Xin Tong
111762ddd0 Fix typo. NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291178 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 21:40:08 +00:00
Teresa Johnson
a4ca999339 ThinLTO: add early "dead-stripping" on the Index
Summary:
Using the linker-supplied list of "preserved" symbols, we can compute
the list of "dead" symbols, i.e. the one that are not reachable from
a "preserved" symbol transitively on the reference graph.
Right now we are using this information to mark these functions as
non-eligible for import.

The impact is two folds:
- Reduction of compile time: we don't import these functions anywhere
  or import the function these symbols are calling.
- The limited number of import/export leads to better internalization.

Patch originally by Mehdi Amini.

Reviewers: mehdi_amini, pcc

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D23488

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291177 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 21:34:18 +00:00
Joerg Sonnenberger
44b0ebe8a3 PR 31534: When emitting both DWARF unwind tables and debug information,
do not use .cfi_sections. This requires checking if any non-declaration
function in the module needs an unwind table.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291172 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 20:55:28 +00:00
Michael Kuperstein
82d65fbb46 [LICM] Allow promotion of some stores that are not guaranteed to execute.
Promotion is always legal when a store within the loop is guaranteed to execute.

However, this is not a necessary condition - for promotion to be memory model
semantics-preserving, it is enough to have a store that dominates every exit
block. This is because if the store dominates every exit block, the fact the
exit block was executed implies the original store was executed as well.

Differential Revision: https://reviews.llvm.org/D28147


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291171 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 20:42:06 +00:00
Matthias Braun
4700463eb1 CodeGen: Assert that liveness is up to date when reading block live-ins.
Add an assert that checks whether liveins are up to date before they are
used.

- Do not print liveins into .mir files anymore in situations where they
  are out of date anyway.
- The assert in the RegisterScavenger is superseded by the new one in
  livein_begin().
- Skip parts of the liveness updating logic in IfConversion.cpp when
  liveness isn't tracked anymore (just enough to avoid hitting the new
  assert()).

Differential Revision: https://reviews.llvm.org/D27562

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291169 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 20:01:19 +00:00
Evgeniy Stepanov
795e15e398 Revert "Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")"
Summary: This reverts commit r291144. It breaks build bots.

http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-autoconf/builds/3270, http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fuzzer/builds/2058

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp:1638:12: error: could not convert ‘(const unsigned int*)(& Variants)’ from ‘const unsigned int*’ to ‘llvm::ArrayRef<unsigned int>’
     return Variants;

Reviewers: eugenis, tstellarAMD

Patch by Alex Shlyapnikov.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D28372

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291168 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 19:51:13 +00:00
Simon Pilgrim
38716ac7b5 [CostModel][X86] Move vXi32 MUL costs into existing tables. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291165 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 19:42:43 +00:00
Simon Pilgrim
7c5fe202d7 Remove trailing whitespace. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291163 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 19:24:25 +00:00
Simon Pilgrim
a04ecdd76e [CostModel][X86] Reordered SSE42 arithmetic cost LUT into descending order. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291162 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 19:19:39 +00:00
Simon Pilgrim
688489139f [CostModel][X86] Move vXi64 MUL costs into existing tables. NFCI.
Removes need for yet another LUT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291158 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 19:01:50 +00:00
Andrew Kaylor
6fe2c0c099 [LICM] Small update to note changes made in hoistRegion
Differential Revision: https://reviews.llvm.org/D28363



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291157 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 18:53:24 +00:00
Simon Pilgrim
944aa53645 [CostModel][X86] Strip unused 256-bit vector shift costs. NFCI.
Remove SSE2 256-bit entries - AVX targets will have used the SSE42 costs instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291152 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 18:36:48 +00:00
Sanjay Patel
2a20870a9f [x86] add test to show bug in select lowering; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291151 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 18:35:44 +00:00
Simon Pilgrim
6c924280fe [CostModel][X86] Include the cost of 256-bit upper subvector extract/insertion in AVX1 v4i64 MUL
Matches other MUL/ADD/SUB 256-bit case on AVX1

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291149 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 18:20:25 +00:00
Joerg Sonnenberger
896b19d30a Typo
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291147 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 17:59:22 +00:00
Simon Pilgrim
46a2104916 [CostModel][X86] Merged SK_PermuteSingleSrc/SK_PermuteTwoSrc into common shuffle cost LUTs. NFCI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291146 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 17:56:19 +00:00
Matt Arsenault
5bd3cb572f Reapply r291025 ("AMDGPU: Remove unneccessary intermediate vector")
Arrays are supposed to be static const

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291144 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 17:36:11 +00:00
Chad Rosier
1c1849cdd8 [AArch64][CostModel] Add coverage for bswap intrinsics.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291140 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 16:55:32 +00:00
Justin Lebar
a4679c0caf [Docs] Update docs to indicate that CUDA compilation is supported on Windows.
Subscribers: cfe-commits, llvm-commits

Differential Revision: https://reviews.llvm.org/D28326

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291139 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 16:54:28 +00:00
Xin Tong
731745ee41 Remove a unnecessary hasLoopInvariantOperands check in loop sink.
Summary:
Preheader instruction's operands will always be invariant w.r.t. the loop which its the preheader
for.

Memory aliases are handled in canSinkOrHoistInst.

Reviewers: danielcdh, davidxl

Subscribers: mzolotukhin, llvm-commits

Differential Revision: https://reviews.llvm.org/D28270

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291132 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 16:52:37 +00:00
Zvi Rackover
34ed20a8ab [X86] Add test cases that cover pr31551. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291127 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 16:48:28 +00:00
Sanjay Patel
1326ed9512 less braces; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291126 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 16:47:32 +00:00
Simon Pilgrim
2cf83fd91e [CostModel][X86] Add support for broadcast shuffle costs
Currently only for broadcasts with input and output of the same width.

Differential Revision: https://reviews.llvm.org/D27811

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291122 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 15:56:08 +00:00
Zvi Rackover
b021632bce [X86] Optimize vector shifts with variable but uniform shift amounts
Summary:
For instructions such as PSLLW/PSLLD/PSLLQ a variable shift amount may be passed in an XMM register.
The lower 64-bits of the register are evaluated to determine the shift amount.
This patch improves the construction of the vector containing the shift amount.

Reviewers: craig.topper, delena, RKSimon

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28353

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291120 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 15:11:43 +00:00
Teresa Johnson
f6f4d232fd [ThinLTO] Add parenthesis as per build warning
Fixes a warning about "||" and "&&" due to r291108.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291119 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 15:10:10 +00:00
Chad Rosier
213f249d8d [AArch64] Remove mcpu option as this test is not target specific. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291117 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 15:05:03 +00:00
Tony Jiang
617a3550a9 [PowerPC] Implement missing ISA 2.06 instructions.
Instructions: fctidu[.], fctiwu[.], ftdiv, ftsqrt are not implemented. Implement
them and add corresponding test cases in this patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291116 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 15:00:45 +00:00
Teresa Johnson
0afe3ab0be [ThinLTO] Use DenseSet instead of SmallPtrSet for holding GUIDs
Should fix some more bot failures from r291108.
This should have been a DenseSet, since GUID is not a pointer type.
It caused some bots to fail, but for some reason I wasnt't getting a
build failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291115 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:59:56 +00:00
Simon Pilgrim
281d15cdbf Wdocumentation fix
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291114 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:58:54 +00:00
Chad Rosier
c8deff8e27 [AArch64] Remove unused arguments from tests. NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291112 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:48:53 +00:00
Teresa Johnson
05a63063fd [ThinLTO] Update new ModuleSummaryIndexYAML.h for r291108
Should fix bot failures due to r291108 which happened due to a
change required in ModuleSummaryIndexYAML.h which was just added in
r291069.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291111 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:40:15 +00:00
Simon Pilgrim
8e5a39580d [CostModel][X86] Pulled out common type legalization code
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291109 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:33:32 +00:00
Teresa Johnson
e4e6279a08 [ThinLTO] Subsume all importing checks into a single flag
Summary:
This adds a new summary flag NotEligibleToImport that subsumes
several existing flags (NoRename, HasInlineAsmMaybeReferencingInternal
and IsNotViableToInline). It also subsumes the checking of references
on the summary that was being done during the thin link by
eligibleForImport() for each candidate. It is much more efficient to
do that checking once during the per-module summary build and record
it in the summary.

Reviewers: mehdi_amini

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28169

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291108 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:32:16 +00:00
Mohammed Agabaria
6bf7471dbc Currently isLikelyComplexAddressComputation tries to figure out if the given stride seems to be 'complex' and need some extra cost for address computation handling.
This code seems to be target dependent which may not be the same for all targets.
Passed the decision whether the given stride is complex or not to the target by sending stride information via SCEV to getAddressComputationCost instead of 'IsComplex'.

Specifically at X86 targets we dont see any significant address computation cost in case of the strided access in general.

Differential Revision: https://reviews.llvm.org/D27518



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291106 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 14:03:41 +00:00
Kristof Beyls
f7936705bf [GlobalISel] Add support for address-taken basic blocks
To make this work, pointers from the MachineBasicBlock to the LLVM-IR-level
basic blocks need to be initialized, as the AsmPrinter uses this link to be
able to print out labels for the basic blocks that are address-taken.

Most of the changes in this commit are about adapting existing tests to include
the basic block name that is now printed out in the MIR format, now that the
name becomes available as the link to the LLVM-IR basic block is initialized.
The relevant test change for the functionality added in this patch are the
added "(address-taken)" strings in
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll.

Differential Revision: https://reviews.llvm.org/D28123



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291105 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 13:27:52 +00:00
Anmol P. Paralkar
b1151ef50b [doc] Fix minor grammatical error in Phabricator.rst
Summary: Test commit, fix minor grammatical error in Phabricator.rst

Reviewers: delcypher

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D28214

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291101 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 13:08:14 +00:00
Kristof Beyls
3c2073e562 [GlobalISel] Add support for switch statements
This commit does this using a trivial chain of conditional branches.  In the
future, we probably want to reuse the optimized switch lowering used in
SelectionDAG.

Differential Revision: https://reviews.llvm.org/D28176



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291099 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 11:28:51 +00:00
Kristof Beyls
44e43a64a6 [GlobalISel] Fix AArch64 ICMP instruction selection
Differential Revision: https://reviews.llvm.org/D28175



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291097 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 10:16:08 +00:00
Mohammed Agabaria
030c24dcda [Test Commit] fixing some format issue in X86TTI to match clang-format output.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291095 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 09:51:02 +00:00
Elena Demikhovsky
25d43b725a AVX-512: Optimized pattern for truncate with unsigned saturation.
DAG patterns optimization: truncate + unsigned saturation supported by VPMOVUS* instructions in AVX-512.
Differential revision: https://reviews.llvm.org/D28216


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291092 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 08:21:09 +00:00
Saleem Abdulrasool
388e476326 test: remove unnecessary triple argument
This test is entirely target agnostic.  Avoid the triple to repair the
build bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291088 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 06:30:12 +00:00
Craig Topper
555794f9b1 [X86] Add Intel Kaby Lake model numbers to getHostCPUName aliased to "skylake" since there are no feature differences.
Model numbers found here http://www.sandpile.org/x86/cpuid.htm

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291086 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 05:57:27 +00:00
Saleem Abdulrasool
50116a25c6 MC: support passing search paths to the IAS
This is needed to support inclusion in inline assembly via the
`.include` directive.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291085 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 05:56:39 +00:00
Craig Topper
6974a461b4 [X86] Change getHostCPUName to report Intel model 0x4e as "skylake" instead of "skylake-avx512". Add the proper 0x55 model for "skylake-avx512".
Summary:
Intel's i5-6300U CPU is reporting to have a model id of 78 (4e).
The Host detection assumes that to be Skylake Xeon (with AVX512 support),
instead of a normal Skylake machine.

Patch by: Valentin Churavy

Reviewers: nalimilan, craig.topper

Subscribers: hfinkel, tkelman, craig.topper, nalimilan, llvm-commits

Differential Revision: https://reviews.llvm.org/D28221

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291084 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 05:47:29 +00:00
Peter Collingbourne
87a14201c5 Tentative fix for modules build.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291079 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 04:40:09 +00:00
Kostya Serebryany
3abdb9d382 [libFuzzer] use /tmp (or $TMPDIR, if present) to store temp files during merge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291078 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 04:32:19 +00:00
Peter Collingbourne
0e1ad99844 Fix build bots.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291073 91177308-0d34-0410-b5e6-96231b3b80d8
2017-01-05 04:00:09 +00:00