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5 Commits

Author SHA1 Message Date
Matt Arsenault
cb0402e9a4 R600: Expand mul24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209458 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:24 +00:00
Matt Arsenault
21851f9adb R600: Expand mad24 for GPUs without it 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209457 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:20 +00:00
Matt Arsenault
f49da4338a R600: Add intrinsics for mad24 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@209456 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-05-22 18:00:15 +00:00
Tom Stellard
5c9bb7119a R600: Match 24-bit arithmetic patterns in a Target DAGCombine 
Moving these patterns from TableGen files to PerformDAGCombine()
should allow us to generate better code by eliminating unnecessary
shifts and extensions earlier.

This also fixes a bug where the MAD pattern was calling
SimplifyDemandedBits with a 24-bit mask on the first operand
even when the full pattern wasn't being matched.  This occasionally
resulted in some instructions being incorrectly deleted from the
program.

v2:
  - Fix bug with 64-bit mul

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205731 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-04-07 19:45:41 +00:00
Tom Stellard
9958475129 R600: Reorganize tablegen instruction definitions 
Each GPU family now has its own file.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@204615 91177308-0d34-0410-b5e6-96231b3b80d8
 2014-03-24 16:07:25 +00:00