158200 Commits

Author SHA1 Message Date
Craig Topper
411b939c3c [X86] Group setOperationActions related to vXi1 masks together. NFCI
Previously they were sort of interleaved in with XMM/YMM/ZMM action related code.

Trying to separate things so its easier to split 512-bit vectors later.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320781 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 01:03:42 +00:00
Craig Topper
8ffae718f0 [X86] Make ISD::INSERT_SUBVECTOR v8i1 legal with AVX512F because we should be custom lowering inserting v1i1 into v8i1 under this.
I don't have a test case at the moment. Just noticed while auditing things.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320780 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 01:03:40 +00:00
Craig Topper
9a06d0d624 [X86] Move some of the hasVLX qualified code out of the main hasAVX512 block in the X86ISelLowering constructor. NFCI
Move it into the separate hasVLX block later in the constructor.

I'm trying to separate 128/256 and 512-bit related code so we can eventually qualify the hasAVX512 block with support for 512-bit vectors required by the prefer-vector-width feature support being talked about in D41096.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320779 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 01:03:38 +00:00
Saleem Abdulrasool
055a3e3225 FastISel: support no-PLT PIC calls on ELF x86_64
Add support for properly handling PIC code with no-PLT.  This equates to
`-fpic -fno-plt -O0` with the clang frontend.  External functions are
marked with nonlazybind, which must then be indirected through the GOT.
This allows code to be built without optimizations in PIC mode without
going through the PLT.  Addresses PR35653!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320776 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 00:32:09 +00:00
Zachary Turner
1764ef1f3a Don't crash in llvm-pdbutil when dumping TypeIndexes with high bit set.
This is a special code that indicates that it's a function id.
While I'm still not certain how to interpret these, we definitely
should *not* be using these values as indices into an array directly.
For now, when we encounter one of these, just print the numeric value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320775 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 00:27:49 +00:00
Sam Clegg
5334180cf2 [WebAssembly] Implement @llvm.global_ctors and @llvm.global_dtors
Summary:
- lowers @llvm.global_dtors by adding @llvm.global_ctors
  functions which register the destructors with `__cxa_atexit`.
- impements @llvm.global_ctors with wasm start functions and linker metadata

See [here](https://github.com/WebAssembly/tool-conventions/issues/25) for more background.

Subscribers: jfb, dschuff, mgorny, jgravelle-google, aheejin, sunfish

Differential Revision: https://reviews.llvm.org/D41211

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320774 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 00:17:10 +00:00
Don Hinton
d7cf6c74e2 [debuginfo] Remove obsolete test_debuginfo.pl that was moved to debuginfo-tests.
Summary:
Now that r320495, "[debuginfo-tests] Support moving
debuginfo-tests to llvm/projects," has landed, which includes a local
copy of test_debuginfo.pl, remove the obsolete copy.

Reviewers: zturner, aprantl

Reviewed By: aprantl

Subscribers: llvm-commits, JDevlieghere

Differential Revision: https://reviews.llvm.org/D41260

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320771 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-15 00:06:26 +00:00
David Blaikie
0584169775 Remove a non-modular header (& inline it into its one use)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320768 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 23:45:58 +00:00
Quentin Colombet
9f7a094913 [TableGen][GlobalISel] Add a common class for all PredicateMatcher
NFC.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320767 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 23:44:07 +00:00
George Burgess IV
f1cb8efede [ProfileData] Use a different data structure to save memory.
This change swaps FunctionSamples to a std::map. This saves us around
17% of the memory required to parse sample profiles. To put hard numbers
on this, clang now eats around 1.3GB of RAM instead of 1.6GB while
parsing a 50MB profile.

The CPU time taken by a large profile merge (3.1GB of data across 226
files) is also reduced by ~11% by this patch (1:09.08 vs 1:01.11).

This was split out at the request of reviewers in D41152.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320764 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 23:32:57 +00:00
Evandro Menezes
5ab8b4581e [Unit][AArch64] Additional tests for target parsing
Add Exynos M2/M3 to extension check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320762 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 23:13:04 +00:00
Evandro Menezes
e615040107 [AArch64] Test patch
Fix formatting by adding a missing blank line to test new network setup.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320760 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 23:06:18 +00:00
Adrian Prantl
4fddb015f4 EmitFuncArgumentDbgValue: Prefer stack slots over registers for stack arguments
While investigating LLVM PR22316 (http://llvm.org/bugs/show_bug.cgi?id=22316)
I started wondering if it were not always preferable to emit the
initial DBG_VALUEs for stack arguments as FI locations instead of
describing the first register they get copied into. The advantage of
doing this is that the arguments will be available as soon as the
stack is setup. As illustrated by the testcase in the PR, the first
copy of the FI into a register may be sunk by MachineSink.cpp into a
later basic block. By describing the argument on the stack, we nicely
circumvent this problem.

<rdar://problem/19583723>

Differential Revision: https://reviews.llvm.org/D41135

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320758 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 22:55:06 +00:00
Craig Topper
696d9a21a9 [X86] Remove an unnecessary SmallVector that was collecting chains for two SDNode's we're still holding SDValues for. NFCI
We can just get the chains from those SDValues to create the TokenFactor.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320757 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 22:50:10 +00:00
Matt Arsenault
45d0bf280d TLI: Allow using PSV for intrinsic mem operands
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320756 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 22:34:10 +00:00
Zachary Turner
ece9b23b54 Fix many -Wsign-compare and -Wtautological-constant-compare warnings.
Most of the -Wsign-compare warnings are due to the fact that
enums are signed by default in the MS ABI, while the
tautological comparison warnings trigger on x86 builds where
sizeof(size_t) is 4 bytes, so N > numeric_limits<unsigned>::max()
is always false.

Differential Revision: https://reviews.llvm.org/D41256

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320750 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 22:07:03 +00:00
Sanjay Patel
7034870f30 [SimplifyCFG] don't sink common insts too soon (PR34603)
This should solve:
https://bugs.llvm.org/show_bug.cgi?id=34603
...by preventing SimplifyCFG from altering redundant instructions before early-cse has a chance to run.
It changes the default (canonical-forming) behavior of SimplifyCFG, so we're only doing the
sinking transform later in the optimization pipeline.

Differential Revision: https://reviews.llvm.org/D38566


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320749 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 22:05:20 +00:00
Matt Arsenault
a40d3af28e DAG: Expose all MMO flags in getTgtMemIntrinsic
Rather than adding more bits to express every
MMO flag you could want, just directly use the
MMO flags. Also fixes using a bunch of bool arguments to
getMemIntrinsicNode.

On AMDGPU, buffer and image intrinsics should always
have MODereferencable set, but currently there is no
way to do that directly during the initial intrinsic
lowering.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320746 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 21:39:51 +00:00
Krzysztof Parzyszek
a9bb60c600 [Hexagon] Generate HVX code for comparisons and selects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320744 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 21:28:48 +00:00
Sam Clegg
e1acb56f11 [WebAssembly] Add support for init functions linking metadata
Summary:
This change lays the groundwork lowering of @llvm.global_ctors
and @llvm.global_dtors for the wasm object format.  Some parts
of this patch are subset of: https://reviews.llvm.org/D40759

See https://github.com/WebAssembly/tool-conventions/issues/25

Subscribers: jfb, dschuff, jgravelle-google, aheejin, sunfish

Differential Revision: https://reviews.llvm.org/D41208

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320742 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 21:10:03 +00:00
Zachary Turner
00bb3b5609 Revert "Fix isPodLike for MSVC and use it in TypeHashing."
This reverts commit ac5edc198eb612f82293850c3488042708b1c5fa.

Apparently this doesn't cover all the bases, so some compilers
and standard libraries still think this is not trivially copyable
even though it is.  Reverting this back to an MSVC-only check for
now so that at least we have some coverage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320739 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 19:59:10 +00:00
Zachary Turner
1fb1af18d2 Fix isPodLike for MSVC and use it in TypeHashing.
This should be a better check than using is_trivially_copyable
behind an #ifdef _MSC_VER.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320737 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 19:41:28 +00:00
Guozhi Wei
44388667e9 [SLPVectorizer] Don't ignore scalar extraction instructions of aggregate value
In SLPVectorizer, the vector build instructions (insertvalue for aggregate type) is passed to BoUpSLP.buildTree, it is treated as UserIgnoreList, so later in cost estimation, the cost of these instructions are not counted. 
For aggregate value, later usage are more likely to be done in scalar registers, either used as individual scalars or used as a whole for function call or return value. Ignore scalar extraction instructions may cause too aggressive vectorization for aggregate values, and slow down performance. So for vectorization of aggregate value, the scalar extraction instructions are required in cost estimation.

Differential Revision: https://reviews.llvm.org/D41139



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320736 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 19:35:43 +00:00
Zachary Turner
b9a44ec3ca Only use is_trivially_copyable if we know it's safe to do so.
Apparently this isn't present on older versions of libstdc++, so
it causes some builds to fail.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320733 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 19:11:28 +00:00
Krzysztof Parzyszek
a3a5536590 Add MVT::v128i1, NFC
Hexagon HVX has type v128i8, comparing two vectors of that type will
produce v128i1 types in SelectionDAG.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320732 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 19:05:21 +00:00
Adam Nemet
71f21a219a [opt-viewer] Render utf-8 characters properly in the generated HTML
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320729 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:55:33 +00:00
Paul Robinson
1efcc42007 [MC] Allow .file directives to be out-of-order
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320727 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:46:43 +00:00
Adam Nemet
747f7a4def [opt-viewer] Support unicode characters in function names
This is a Swift feature.  The output stream for the index page and the source
HTML page is utf-8 now.

The next patch will add the HTML magic to properly render these characters in
the browser.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320725 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:42:42 +00:00
Shoaib Meenai
18fcbf52eb [cmake] Only attempt to install MSVC system libraries on Windows
Newer versions of CMake (I'm on 3.10, but I believe 3.9 behaves the same
way) attempt to query the system for information about the VS 2017
install. Unfortunately, this query fails on non-Windows systems:

  cmake_host_system_information does not recognize <key> VS_15_DIR

CMake isn't going to find these system libraries on non-Windows anyway
(and we were previously silencing the resultant warnings in our
cross-compilation toolchain), so it makes sense to just omit the
attempted installation entirely on non-Windows.

Differential Revision: https://reviews.llvm.org/D41220

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320724 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:41:49 +00:00
Craig Topper
f74c3ebbfb [X86] Don't zero the upper bits of the k-register before extracting a single bit from a vXi1.
This doesn't match the semantics of the extract_vector_elt operation. Nothing downstream knows the bits were zeroed so they still get masked or sign extended after the extrat anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320723 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:35:25 +00:00
Krzysztof Parzyszek
7c66ebefee [Hexagon] Remove vectors of i64 from valid HVX types
HVX does not support operations on 64-bit integers.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320722 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:35:24 +00:00
Zachary Turner
cc1c188e61 Fix error due to missing includes.
While I'm pushing cleanup changes, this also fixes a few warnings
related to extraneous semicolons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320720 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:20:23 +00:00
Zachary Turner
6b1df4d6a7 [COFF] Teach LLD to use the COFF .debug$H section.
This adds the /DEBUG:GHASH option to LLD which will look for
the existence of .debug$H sections in linker inputs and use them
to accelerate type merging.  The clang-cl side has already been
added, so this completes the work necessary to begin experimenting
with this feature.

Differential Revision: https://reviews.llvm.org/D40980

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320719 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:07:04 +00:00
Geoff Berry
c04e9d0dbf [ARM] Fix isRenamable flag setting on expanded VSTMDIA opcode.
Fixes expensive-check ARM buildbot failure.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320718 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 18:06:25 +00:00
Gadi Haber
9ad242e7fa [X86][AVX][AVX2]: Adding full coverage of MC encoding for the AVX, AVX2 isa set.<NFC>
NFC.
Adding MC regressions tests to cover the AVX and AVX2 ISA sets.
This patch is part of a larger task to cover MC encoding of all X86 ISA Sets.
See revision: https://reviews.llvm.org/D39952

Reviewers: zvi, RKSimon, aymanmus, m_zuckerman
Differential Revison: https://reviews.llvm.org/D40287

Change-Id: I304687a2b7abb473f79de99c31fc55c97b2662da

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320716 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 16:46:47 +00:00
Simon Dardis
e8153722a3 [mips] Update some tests before posting a patch, NFC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320715 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 16:42:04 +00:00
Yaxun Liu
92d81a8d46 Revert CodeGen: Fix assertion in machine inst sheduler due to llvm.dbg.value
This commit might have caused regression on ppc64. Revert it to verify that.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320712 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 16:12:04 +00:00
Sander de Smalen
9a94efd832 Re-commit: [TableGen] AsmMatcher: Fix bug with reported diagnostic for operand.
Summary:
The generated diagnostic by the AsmMatcher isn't always applicable to the AsmOperand.

This is because the code will only update the diagnostic if it is more 
specific than the previous diagnostic. However, when having validated
operands and 'moved on' to a next operand (for some instruction/alias for
which all previous operands are valid), if the diagnostic is InvalidOperand,
than that should be set as the diagnostic, not the more specific message
about a previous operand for some other instruction/alias candidate.

(Re-committed with an extra whitespace in SVEInstrFormats.td to trigger rebuild 
of AArch64GenAsmMatcher.inc, since the llvm-clang-x86_64-expensive-checks-win
builder does not seem to rebuild AArch64GenAsmMatcher.inc with the
newly built TableGen due to a missing dependency somewhere (see:
http://lists.llvm.org/pipermail/llvm-dev/2017-December/119555.html))

Reviewers: craig.topper, olista01, rengolin, stoklund

Reviewed By: olista01

Subscribers: javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40011



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320711 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 16:09:48 +00:00
Eugene Leviant
9b53469bfe [LLVMgold] Use platform dependent extension in tests
Differential revision: https://reviews.llvm.org/D41238


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320710 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 15:59:05 +00:00
Simon Dardis
6ca3095cfb [mips] Add partial support for R6 in the long branch pass
MIPSR6 introduced several new jump instructions and deprecated
the use of the 'j' instruction. For microMIPS32R6, 'j' was removed
entirely and it only has non delay slot jumps.

This patch adds support for MIPSR6 by using some R6 instructions--
'bc' instead of 'j', 'jic $reg, 0' instead of 'jalr $zero, $reg'--
and modifies the sequences not to use delay slots for R6.

Reviewers: atanasyan

Reviewed By: atanasyan

Subscribers: dschuff, arichardson, llvm-commits

Differential Revision: https://reviews.llvm.org/D40786


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320703 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 14:55:25 +00:00
Bjorn Pettersson
e7acf09de4 [ScalarEvolution] Fix base condition in isNormalAddRecPHI.
Summary:
The function is meant to recurse until it comes upon the
phi it's looking for. However, with the current condition,
it will recurse until it finds anything _but_ the phi.

The function will even fail for simple cases like:
  %i = phi i32 [ %inc, %loop ], ...
  ...
  %inc = add i32 %i, 1

because the base condition will not happen when the phi
is recursed to, and the recursion will end with a 'false'
result since the previous instruction is a phi.

Reviewers: sanjoy, atrick

Reviewed By: sanjoy

Subscribers: Ka-Ka, bjope, llvm-commits

Committing on behalf of: Bevin Hansson (bevinh)

Differential Revision: https://reviews.llvm.org/D40946

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320700 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 14:47:52 +00:00
Haicheng Wu
ed49714687 [InlineCost] Tracking Values through PHI Nodes
This patch fix this FIXME in visitPHI()

FIXME: We should potentially be tracking values through phi nodes,
especially when they collapse to a single value due to deleted CFG edges
during inlining.

Differential Revision: https://reviews.llvm.org/D38594

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320699 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 14:36:18 +00:00
Benjamin Kramer
f30ce39f3a Revert "[DAGCombine] Move AND nodes to multiple load leaves"
This reverts commit r320679. Causes miscompiles.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320698 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 14:03:07 +00:00
Andrew V. Tischenko
e3c92f3b0d Any Target Asm comments should start from MachineInstr::TAsmComments value.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320693 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 12:07:11 +00:00
Omer Paparo Bivas
87c8e44045 Inserting several lit tests to reflect current behaviour
Change-Id: I1b8188dc3c6c7c0f455715364ece7d35ef485f2f

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320692 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 12:00:04 +00:00
Michael Zuckerman
74c2e95576 [AVX512] Adding support for load truncate store of I1
store operation on a truncated memory (load) of vXi1 is poorly supported by LLVM and most of the time end with an assertion.
This patch fixes this issue.

Differential Revision: https://reviews.llvm.org/D39547

Change-Id: Ida5523dd09c1ad384acc0a27e9e59273d28cbdc9

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320691 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 11:55:50 +00:00
Simon Pilgrim
9e819d59ee [X86] Add FMA4 schedule tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320690 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 11:40:54 +00:00
Simon Pilgrim
d355ea7abc [X86] Add FMA3 schedule tests
Rewrote to use inline asm for full coverage

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320689 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 11:30:01 +00:00
Fedor Sergeev
bfac46c5f4 [PM][InstCombine] fixing omission of AliasAnalysis in new-pass-manager's version of InstCombine
Summary:
Passing AliasAnalysis results instead of nullptr appears to work just fine.
A couple new-pass-manager tests updated to align with new order of analyses.

Reviewers: chandlerc, spatel, craig.topper

Reviewed By: chandlerc

Subscribers: mehdi_amini, eraman, llvm-commits

Differential Revision: https://reviews.llvm.org/D41203

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320687 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 10:36:31 +00:00
Fedor Sergeev
45b92d7fda Remove redundant includes from lib/Target/AArch64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320686 91177308-0d34-0410-b5e6-96231b3b80d8
2017-12-14 10:36:20 +00:00