122974 Commits

Author SHA1 Message Date
Igor Laevsky
48b3c93735 [MemorySanitizer] NFC. Do not use GET_INTRINSIC_MODREF_BEHAVIOR table.
It is now possible to infer intrinsic modref behaviour purely from intrinsic attributes.
This change will allow to completely remove GET_INTRINSIC_MODREF_BEHAVIOR table.

Differential Revision: http://reviews.llvm.org/D13907



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250860 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 21:33:30 +00:00
Simon Pilgrim
cf2cac0bd9 [X86][SSE] Add 256-bit vector bit rotation tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250853 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 20:27:23 +00:00
Duncan P. N. Exon Smith
1e221d5c2c bugpoint: Remove implicit ilist iterator conversions, NFC
This is the last of the implicit ilist iterator conversions in LLVM.
Still up for debate whether we let these bitrot back:
http://lists.llvm.org/pipermail/llvm-dev/2015-October/091617.html

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250852 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 19:36:39 +00:00
Krzysztof Parzyszek
4465351205 [Hexagon] Capture aggregate variables by reference, not value
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250851 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 19:33:46 +00:00
Krzysztof Parzyszek
014b76cd0f [Hexagon] Do not fall-through if there is no CFG edge
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250850 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 19:30:21 +00:00
Krzysztof Parzyszek
cdc93cb36f [Hexagon] Use symbolic name for subregister instead of hardcoded number
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250849 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 19:26:36 +00:00
Krzysztof Parzyszek
e7b5e3c89d [Hexagon] Change Based->Base in getBasedWithImmOffset
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250848 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 19:21:05 +00:00
Krzysztof Parzyszek
1f2d4d356d [Hexagon] Remove the remnants of isConstExtProfitable
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250845 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 19:04:53 +00:00
Duncan P. N. Exon Smith
70f8c2049f unittests: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250843 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 18:30:20 +00:00
Duncan P. N. Exon Smith
00f8d5fdf7 llvm-diff: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250842 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 18:17:05 +00:00
Chris Bieneman
20263fdbfb [CMake] All the checks for if LLVM_VERSION_* variables are set need to be if(DEFINED ...)
This is because if you set one of the variables to 0, if(NOT ...) is true, which isn't what you actually want. Should have thought that through better the first time.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250841 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 18:16:37 +00:00
Chris Bieneman
e5b90ccacc [CMake] Refactor subdirectory inclusion code to take a project name.
Summary:
This refactoring makes some of the code used to control including subdirectories parameterized so it can be re-used elsewhere.

Specifically I want to re-use this code in clang to be able to turn off specific tool subdirectories.

Reviewers: chapuni, filcab, bogner, Bigcheese

Subscribers: emaste, llvm-commits

Differential Revision: http://reviews.llvm.org/D13783

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250835 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 16:42:58 +00:00
Artyom Skrobov
7d55a0bab7 Two switch blocks in VectorLegalizer::LegalizeOp already have a
default: llvm_unreachable("This action is not supported yet!");

-- so I'm adding one to the third switch block, too.

This is a follow-up fix for http://reviews.llvm.org/D13862




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250830 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 15:06:37 +00:00
Jonas Paulsson
23d79658db [SystemZ] Use LivePhysRegs helper class in SystemZShortenInst.cpp.
Don't use home brewed liveness tracking code for phys regs, since
this class does the job.

Reviewed by Ulrich Weigand.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250829 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 15:05:58 +00:00
Jonas Paulsson
53675f88a1 [SystemZ] Comment fix in test/CodeGen/SystemZ/fp-cmp-05.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250828 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 15:05:54 +00:00
Artyom Skrobov
190815e2ea Adding support for TargetLoweringBase::LibCall
Summary:
TargetLoweringBase::Expand is defined as "Try to expand this to other ops,
otherwise use a libcall." For ISD::UDIV and ISD::SDIV, the choice between
the two possibilities was defined in a rather convoluted way:

- if DIVREM is legal, expand to DIVREM
- if DIVREM has a custom lowering, expand to DIVREM
- if DIVREM libcall is defined and a remainder from the same division is
  computed elsewhere, expand to a DIVREM libcall
- else, expand to a DIV libcall

This had the undesirable effect that if both DIV and DIVREM are implemented
as libcalls, then ISD::UDIV and ISD::SDIV are expanded to the heavier DIVREM
libcall, even when the remainder isn't used.

The new code adds a new LegalizeAction, TargetLoweringBase::LibCall, so that
backends can directly control whether they prefer an expansion or a conversion
to a libcall. This makes the generic lowering code even more generic,
allowing its reuse in a wider range of target-specific configurations.

The useful effect is that ARM backend will now generate a call
to __aeabi_{i,u}div rather than __aeabi_{i,u}divmod in cases where
it doesn't need the remainder. There's no functional change outside
the ARM backend.

Reviewers: t.p.northover, rengolin

Subscribers: t.p.northover, llvm-commits, aemerson

Differential Revision: http://reviews.llvm.org/D13862

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250826 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 13:14:52 +00:00
Artyom Skrobov
42c2a81d51 Combining DIV+REM->DIVREM doesn't belong in LegalizeDAG; move it over into DAGCombiner.
Summary:
In addition to moving the code over, this patch amends the DIV,REM -> DIVREM
combining to run on all affected nodes at once: if the nodes are converted
to DIVREM one at a time, then the resulting DIVREM may get legalized by the
backend into something target-specific that we won't be able to recognize
and correlate with the remaining nodes.

The motivation is to "prepare terrain" for D13862: when we set DIV and REM
to be legalized to libcalls, instead of the DIVREM, we otherwise lose the
ability to combine them together. To prevent this, we need to take the
DIV,REM -> DIVREM combining out of the lowering stage.

Reviewers: RKSimon, eli.friedman, rengolin

Subscribers: john.brawn, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D13733



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250825 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 13:06:02 +00:00
Igor Breger
7bbbc5ccde AVX512: Implemented encoding and intrinsics for VPBROADCASTB/W/D/Q instructions.
Differential Revision: http://reviews.llvm.org/D13884

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250819 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 11:56:42 +00:00
Andrea Di Biagio
eb09365c84 [x86] Fix AVX maskload/store intrinsic prototypes.
The mask value type for maskload/maskstore GCC builtins is never a vector of
packed floats/doubles.

This patch fixes the following issues:
1. The mask argument for builtin_ia32_maskloadpd and builtin_ia32_maskstorepd
   should be of type llvm_v2i64_ty and not llvm_v2f64_ty.
2. The mask argument for builtin_ia32_maskloadpd256 and
   builtin_ia32_maskstorepd256 should be of type llvm_v4i64_ty and not
   llvm_v4f64_ty.
3. The mask argument for builtin_ia32_maskloadps and builtin_ia32_maskstoreps
   should be of type llvm_v4i32_ty and not llvm_v4f32_ty.
4. The mask argument for builtin_ia32_maskloadps256 and
   builtin_ia32_maskstoreps256 should be of type llvm_v8i32_ty and not
   llvm_v8f32_ty.

Differential Revision: http://reviews.llvm.org/D13776


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250817 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 11:20:13 +00:00
Keno Fischer
bb5ca273e0 Fix missing INITIALIZE_PASS_DEPENDENCY for AddressSanitizer
Summary: In r231241, TargetLibraryInfoWrapperPass was added to
`getAnalysisUsage` for `AddressSanitizer`, but the corresponding
`INITIALIZE_PASS_DEPENDENCY` was not added.

Reviewers: dvyukov, chandlerc, kcc

Subscribers: kcc, llvm-commits

Differential Revision: http://reviews.llvm.org/D13629

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250813 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 10:13:55 +00:00
Manuel Klimek
1df0e84c25 Make class final to pacify -Wnon-virtual-dtor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250805 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 08:21:01 +00:00
Matt Arsenault
d2643e2ff9 AMDGPU: Add MachineInstr overloads for instruction format tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250797 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 04:35:43 +00:00
Lang Hames
7233876104 [Orc] Make CompileOnDemandLayer::findSymbol call BaseLayer::findSymbol if no
symbol definition is found in the logical dylibs.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250796 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 04:35:02 +00:00
Matt Arsenault
08e1ec066d AMDGPU: Stop reserving v[254:255]
This wasn't doing anything useful. They weren't explicitly used
anywhere, and the RegScavenger ignores reserved registers.

This for some reason caused a random scheduling change in the test.
Getting the check lines to pass is too frustrating, and there's probably
not too much value in checking the vector case's operands N times.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250794 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 03:59:58 +00:00
JF Bastien
175c683f63 WebAssembly: fix call/return syntax.
They are now typeless, unlike other operations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250793 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:26:54 +00:00
Duncan P. N. Exon Smith
3698b0ef55 MSP430: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250792 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:18:39 +00:00
Duncan P. N. Exon Smith
090db0267d AsmParser: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250791 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:12:49 +00:00
Duncan P. N. Exon Smith
e8e219bb51 SystemZ: Remove implicit ilist iterator conversion, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250790 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:12:46 +00:00
Duncan P. N. Exon Smith
a1a3f2d293 XCore: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250788 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:07:42 +00:00
Duncan P. N. Exon Smith
fa3f538fd6 PowerPC: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250787 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:07:37 +00:00
Sanjoy Das
35072eb786 [RS4GC] Remove a redundant linear search, NFCI
Since LiveVariables is uniqued (we just created it from a `DenseSet`),
`FindIndex(LiveVariables, LiveVariables[i])` is always `i`.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250786 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:06:31 +00:00
Sanjoy Das
3d31aca999 [RS4GC] Clean up find_index; NFC
- Bring it up to the LLVM Coding Style
 - Sink it inside `CreateGCRelocates`, which is its only user

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250785 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:06:28 +00:00
Sanjoy Das
66e29d1ed1 [RS4GC] Re-purpose normalizeForInvokeSafepoint; NFC.
`normalizeForInvokeSafepoint` in RewriteStatepointsForGC.cpp, as it is
written today, deals with `gc.relocate` and `gc.result` uses of a
statepoint equally well.  This change documents this fact and adds a
test case.

There is no functional change here -- only documentation of existing
functionality.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250784 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:06:24 +00:00
Sanjoy Das
8293dfd63f [RS4GC] Minor cleanup to normalizeForInvokeSafepoint; NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250783 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 01:06:17 +00:00
Duncan P. N. Exon Smith
2b1499041b Sparc: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250781 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:59:43 +00:00
Duncan P. N. Exon Smith
db991cb068 NVPTX: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250779 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:54:09 +00:00
Duncan P. N. Exon Smith
8525f3a7bc Hexagon: Remove implicit ilist iterator conversions, NFC
There are two things out of the ordinary in this commit.  First, I made
a loop obviously "infinite" in HexagonInstrInfo.cpp.  After checking if
an instruction was at the beginning of a basic block (in which case,
`break`), the loop decremented and checked the iterator for `nullptr` as
the loop condition.  This has never been possible (the prev pointers are
always been circular, so even with the weird ilist/iplist
implementation, this isn't been possible), so I removed the condition.

Second, in HexagonAsmPrinter.cpp there was another case of comparing a
`MachineBasicBlock::instr_iterator` against `MachineBasicBlock::end()`
(which returns `MachineBasicBlock::iterator`).  While not incorrect,
it's fragile.  I switched this to `::instr_end()`.

All that said, no functionality change intended here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250778 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:46:39 +00:00
JF Bastien
9f16772a3d WebAssembly: fix syntax for br_if.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250777 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:37:42 +00:00
Duncan P. N. Exon Smith
97fa27f70e AsmPrinter: Remove implicit ilist iterator conversion, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250776 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:36:08 +00:00
Duncan P. N. Exon Smith
ddeb82cedb Mips: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250769 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:15:20 +00:00
Duncan P. N. Exon Smith
7a225f7f37 CppBackend: Remove implicit ilist iterator conversions, NFC
Mostly just converted to range-based for loops.  May have converted a
couple of extra loops as a drive-by (not sure).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250766 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:06:41 +00:00
Duncan P. N. Exon Smith
2b76674c16 BPF: Remove implicit ilist iterator conversion, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250765 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-20 00:02:50 +00:00
Duncan P. N. Exon Smith
974314ae03 ARM: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250759 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 23:25:57 +00:00
Lang Hames
354229b217 [Orc] Fix MSVC bugs introduced in r250749.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250758 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 23:23:17 +00:00
Duncan P. N. Exon Smith
25622c1340 ObjCARC: Remove implicit ilist iterator conversions, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250756 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 23:20:14 +00:00
Cong Hou
f2558c2db4 Enhance loop rotation with existence of profile data in MachineBlockPlacement pass.
Currently, in MachineBlockPlacement pass the loop is rotated to let the best exit to be the last BB in the loop chain, to maximize the fall-through from the loop to outside. With profile data, we can determine the cost in terms of missed fall through opportunities when rotating a loop chain and select the best rotation. Basically, there are three kinds of cost to consider for each rotation:

1. The possibly missed fall through edge (if it exists) from BB out of the loop to the loop header.
2. The possibly missed fall through edges (if they exist) from the loop exits to BB out of the loop.
3. The missed fall through edge (if it exists) from the last BB to the first BB in the loop chain.

Therefore, the cost for a given rotation is the sum of costs listed above. We select the best rotation with the smallest cost. This is only for PGO mode when we have more precise edge frequencies.

Differential revision: http://reviews.llvm.org/D10717



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250754 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 23:16:40 +00:00
Lang Hames
e61c7b5220 [Orc] Use '= default' for move constructor/assignment as per dblaikie's review.
Thanks Dave!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250749 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 22:49:18 +00:00
Duncan P. N. Exon Smith
989a95d395 Linker: Remove implicit ilist iterator conversion, NFC
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250748 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 22:23:36 +00:00
David Blaikie
36d045a51f Fix -Wdeprecated regarding ORC copying ValueMaterializers
As usual, this is a polymorphic hierarchy without polymorphic ownership,
so simply make the dtor protected non-virtual, protected default copy
ctor/assign, and make derived classes final. The derived classes will
pick up correct default public copy ops (and dtor) implicitly.

(wish I could add -Wdeprecated to the build, but last time I tried it
triggered on some system headers I still need to look into/figure out)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250747 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 22:15:55 +00:00
Michael Liao
2949a6ae04 [InstCombine] Optimize icmp of inc/dec at RHS
Allow LLVM to optimize the sequence like the following:

  %inc = add nsw i32 %i, 1
  %cmp = icmp slt %n, %inc

into:

  %cmp = icmp sle i32 %n, %i

The case is not handled previously due to the complexity of compuation of %n.
Hence, LLVM cannot swap operands of icmp accordingly.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@250746 91177308-0d34-0410-b5e6-96231b3b80d8
2015-10-19 22:08:14 +00:00