Commit Graph

3428 Commits

Author SHA1 Message Date
Joerg Sonnenberger
b85d6905b5 Fix spelling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207982 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 17:58:46 +00:00
Rafael Espindola
bd7cb3a62d Move test to the ARM64 directory.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207972 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 16:14:37 +00:00
Rafael Espindola
260b6b05b9 Convert a CodeGen test into a MC test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207971 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-05 15:34:13 +00:00
Saleem Abdulrasool
a7321a6e53 MC: support FK_SecRel_4 for Windows on ARM
Add handling for FK_SecRel_4 (4-byte section relative relocations).  These are
used by the generation of DWARF debug information (the abbrevations use section
relative relocations).  This will also be used in generation of CodeView line
tables.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207941 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-04 23:13:15 +00:00
Rafael Espindola
930ca98433 Fix pr19645.
The fix itself is fairly simple: move getAccessVariant to MCValue so that we
replace the old weak expression evaluation with the far more general
EvaluateAsRelocatable.

This then requires that EvaluateAsRelocatable stop when it finds a non
trivial reference kind. And that in turn requires the ELF writer to look
harder for weak references.

Last but not least, this found a case where we were being bug by bug
compatible with gas and accepting an invalid input. I reported pr19647
to track it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207920 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-03 19:57:04 +00:00
Saleem Abdulrasool
735f9edde1 MC: place .file records into the correct section
.file records are supposed to have a section identifier of 65534
(IMAGE_SCN_DEBUG) rather than 0.  This is spelt out clearly within the PE/COFF
specification.  Fix this minor oversight with the implementation for support for
.file records.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207851 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-02 17:45:24 +00:00
Rafael Espindola
dbd5d9d0b8 Don't propagate StorageClass and ComplexType to aliases.
This matches gas' behaviour on COFF.

I think that this yak is now sufficiently shaved for aliases with offset
to work.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207786 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 19:02:03 +00:00
Rafael Espindola
23d27597a3 Compute the correct section for zed = foo + 1 in COFF.
This fixes pr19147.

There are a few more related issues to fix, but the testcase in the bug now
passes.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207763 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 13:37:57 +00:00
Rafael Espindola
1b68a68c04 Don't force symbols to be globals in .thumb_set.
We currently force symbols to be globals in .thumb_set. The intent
seems to be that given

.thumb_set foo, bar

we emit an undefined symbol to bar if it is never defined. The side
effect is that we mark bar as global, even if it is defined, which gas
does not.

Producing an undefined reference to bar is a general difference from MC and gas.
For example, given

a = b

gas will produce an undefined reference to b, MC will not. I would be surprised
if any code depends on this, but it it does, we should fix the general
difference, not special case .thumb_set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207757 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:45:43 +00:00
Tim Northover
3c5651a003 AArch64/ARM64: rewrite test to use FileCheck & add ARM64 lines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207754 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:30:01 +00:00
Tim Northover
fadbf53e7e AArch64/ARM64: port basic disassembly tests to ARM64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207753 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:29:56 +00:00
Tim Northover
f2f35a9ca3 AArch64/ARM64: print BFM instructions as BFI or BFXIL
The canonical form of the BFM instruction is always one of the more explicit
extract or insert operations, which makes reading output much easier.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207752 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 12:29:38 +00:00
Richard Barton
8b88679164 Correction to assert statemtent to allow 32-bit unsigned numbers with the top bit set.
This fixes an ARM assembler crash - regression test added.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207747 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 11:37:44 +00:00
Bradley Smith
e29cd17aeb [ARM64] Conditionalize CPU specific system registers on subtarget features
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207742 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 10:25:36 +00:00
Matheus Almeida
4c715625d9 [mips] Move expansion of .cpsetup to target streamer.
Summary:
There are two functional changes:
1) The directive is not expanded for the ASM->ASM code path.
2) If PIC is not set, there's no expansion for the ASM->OBJ code path (same behaviour as GAS).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3482

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207741 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 10:24:46 +00:00
Daniel Sanders
873f87c2de [mips] Removed two-operand alias for sllv, sr[al]v, rotrv, dsllv, dsr[al]v, and drotrv
GAS doesn't actually accept these particular cases.

The mnemonic without the trailing 'v' still supports two-operand aliases.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207740 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 10:08:36 +00:00
Oliver Stannard
5604ab9da4 Record the DWARF version in MCContext
Record the DWARF version in MCContext, and use it when
emitting the dwarf version into the debug info.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207739 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 08:46:02 +00:00
Rafael Espindola
b77f8919bc Start fixing pr19147.
This makes the coff writer compute the correct symbol value for the test in
pr19147. The section is still incorrect, that will be fixed in a followup patch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207728 91177308-0d34-0410-b5e6-96231b3b80d8
2014-05-01 00:10:17 +00:00
James Molloy
d96bbedc6a Move a testcase from ELF to ARM64, incorrectly placed in r207627.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207706 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 21:31:11 +00:00
James Molloy
6f327421c5 Add a testcase for r207627.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207697 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 20:06:26 +00:00
Matheus Almeida
1afb0ccb40 [mips] Add instruction alias (negu).
Summary: negu $reg is equivalent to negu $reg, $reg.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3510

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207673 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:53:49 +00:00
Matheus Almeida
3fa0a85ce8 [mips] Add instruction alias (sltu).
Summary:
The pattern sltu $r1, $r2, $imm is found in handwritten assembly which
is just a shorthand version of sltui $r1, $r2, $imm.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3508

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207671 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:29:56 +00:00
Hans Wennborg
a8febf2283 ELFObjectWriter: deduplicate suffices in strtab
We already do this for shstrtab, so might as well do it for strtab. This
extracts the string table building code into a separate class. The idea
is to use it for other object formats too.

I mostly wanted to do this for the general principle, but it does save a
little bit on object file size. I tried this on a clang bootstrap and
saved 0.54% on the sum of object file sizes (1.14 MB out of 212 MB for
a release build).

Differential Revision: http://reviews.llvm.org/D3533

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207670 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:25:02 +00:00
Tim Northover
b1c1b8a78d ARM64: print fp immediates without using scientific notation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207669 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:34 +00:00
Tim Northover
83286f081d AArch64/ARM64: implement remaining TLS relocations (purely MC).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207668 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:26 +00:00
Tim Northover
50de5e4f57 AArch64/ARM64: add specific diagnostic for MRS/MSR and enable tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207667 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:20 +00:00
Tim Northover
52f60f81d9 AArch64/ARM64: accept and print floating-point immediate 0 as "#0.0"
It's been decided that in the future, the floating-point immediate in
instructions like "fcmeq v0.2s, v1.2s, #0.0" will be canonically "0.0", which
has been implemented on AArch64 already but not ARM64.

This fixes that issue.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207666 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:13:07 +00:00
Matheus Almeida
c3a5ef59e4 [mips] Add instruction alias (dsll and dsrl).
Summary:
The pattern dsll/dsrl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of dsllv/dsrlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3486

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207664 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 16:00:49 +00:00
Rafael Espindola
41fb117905 Relax the test a bit.
It is not relevant where the symbol and section names are stored, just their
values.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207662 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:32:21 +00:00
Rafael Espindola
3dbcd2e69e Rename the test, it is testing the symver directive.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207658 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:27:44 +00:00
Matheus Almeida
6c71a5f6e4 [mips] Add instruction alias (sll and srl).
Summary:
The pattern sll/srl $rd, $rt, $rs is found in handwritten assembly which
is just a shorthand version of sllv/srlv $rd, $rt, $rs.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3483

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207657 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 15:23:04 +00:00
Matheus Almeida
99b44bacab [mips] Update tests with encoding information for slt, slti, sltiu and sltu.
Summary:
Also renamed non-portable register names (e.g. $t2) so that we don't end up
with a different encoding for what appears to be an equivalent instruction.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3505

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207655 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 14:52:57 +00:00
Tim Northover
ee053f4f51 ARM64: enable AArch64's basic-a64-instructions test
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207650 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:10 +00:00
Tim Northover
44a2f5610d ARM64: print lsr instead of lsrv for variable shifts (etc)
The canonical syntax for shifts by a variable amount does not end with 'v', but
that syntax should be supported as an alias (presumably for legacy reasons).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207649 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:07 +00:00
Tim Northover
7870967ba1 ARM64: use 32-bit operations for uxtb & uxth
Testing will be enabled shortly with basic-a64-instructions.s

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207648 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:37:02 +00:00
Tim Northover
bfb7bc89df AArch64/ARM64: copy support for bCC instead of b.CC across.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207646 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:36:56 +00:00
Tim Northover
d805bf8d61 AArch64/ARM64: use HS instead of CS & LO instead of CC.
On instructions using the NZCV register, a couple of conditions have dual
representations: HS/CS and LO/CC (meaning unsigned-higher-or-same/carry-set and
unsigned-lower/carry-clear). The first of these is more descriptive in most
circumstances, so we should print it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207644 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 13:14:03 +00:00
Tim Northover
4e29e3a10a ARM64: accept ELF-relocated load/store insts without a #.
E.g. we print "ldr x0, [x0, :lo12:symbol]" so we need to accept that syntax
too.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207639 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 12:00:20 +00:00
Matheus Almeida
00bdeb4c54 [mips] Add support for .cpload.
Summary:
This directive is used for setting up $gp in the beginning of a function.
It expands to three instructions if PIC is enabled:
lui   $gp, %hi(_gp_disp)
addui $gp, $gp, %lo(_gp_disp)
addu  $gp, $gp, $reg

_gp_disp is a special symbol that the linker sets to the distance between
the lui instruction and the context pointer (_gp).

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3480

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207637 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:28:42 +00:00
Matheus Almeida
737de9db8e [mips] Emit all three relocation operations for each relocation entry on Mips64 big-endian systems.
Summary:
The N64 ABI allows up to three operations to be specified per relocation record
independently of the endianness.

Reviewers: dsanders

Reviewed By: dsanders

Differential Revision: http://reviews.llvm.org/D3529

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207636 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:21:10 +00:00
Tim Northover
ebde5a5e49 ARM64: use hex immediates for movz/movk instructions
Since these are mostly used in "lsl #16", "lsl #32", "lsl #48" combinations to
piece together an immediate in 16-bit chunks, hex is probably the most
appropriate format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207635 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:40 +00:00
Tim Northover
87476b607c ARM64: hexify printing various immediate operands
This is mostly aimed at the NEON logical operations and MOVI/MVNI (since they
accept weird shifts which are more naturally understandable in hex notation).

Also changes BRK/HINT etc, which is probably a neutral change, but easier than
the alternative.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207634 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:28 +00:00
Tim Northover
2a2cce79be ARM64: print canonical syntax for add/sub (imm) instructions.
Since these instructions only accept a 12-bit immediate, possibly shifted left
by 12, the canonical syntax used by the architecture reference manual is "#N {,
lsl #12 }". We should accept an immediate that has already been shifted, (e.g.

Also, print a comment giving the full addend since it can be helpful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207633 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 11:19:15 +00:00
Saleem Abdulrasool
f3ce0c061e ARM: print COFF function header for Windows on ARM
Emit the COFF header when printing out the function.  This is important as the
header contains two important pieces of information: the storage class for the
symbol and the symbol type information.  This bit of information is required for
the linker to correctly identify the type of symbol that it is dealing with.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207613 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-30 06:14:25 +00:00
Joerg Sonnenberger
edc4595472 Parse and create GOT_PREL relocations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207526 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 13:42:02 +00:00
Rafael Espindola
1c5f439f41 Centralize the handling of the thumb bit.
This patch centralizes the handling of the thumb bit around
MCStreamer::isThumbFunc and makes isThumbFunc handle aliases.

This fixes a corner case, but the main advantage is having just one
way to check if a MCSymbol is thumb or not. This should still be
refactored to be ARM only, but at least now it is just one predicate
that has to be refactored instead of 3 (isThumbFunc,
ELF_Other_ThumbFunc, and SF_ThumbFunc).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207522 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-29 12:46:50 +00:00
Rafael Espindola
1c509556ee Add an option for evaluating past symbols.
When evaluating an assembly expression for a relocation, we want to
stop at MCSymbols that are in the symbol table, even if they are variables.
This is needed since the semantics may require that the relocation use them.

That is not the case when computing the value of a symbol in the symbol table.
There are no relocations in this case and we have to keep going until we hit
a section or find out that the expression doesn't have an assembly time
value.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207445 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 20:53:11 +00:00
Rafael Espindola
0af058ff9c Don't include an invalid symbol in the symbol table.
The symbol table itself has no relocations, so it is not possible to represent
things like

a = undefined + 1

With the patch we just omit these variables. That matches the behaviour of the
gnu assembler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207419 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 13:39:57 +00:00
Rafael Espindola
086e9aaa55 List the entire symbol table in this test.
This will allow us to extend this test to show that other symbols don't
show up in the symbol table.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207418 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 13:26:35 +00:00
Rafael Espindola
c074b096d5 Produce an error instead of a crash in an expr we cannot represent.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207414 91177308-0d34-0410-b5e6-96231b3b80d8
2014-04-28 12:40:50 +00:00